2019 08 05 meeting notes

Agenda

• Opens
• Development update for past two weeks

Meeting notes

Participants: Alexey Bader(Intel), Oleg Maslov(Intel), Ronan Keryell(Xilinx), Andrew Gozillon(Xilinx), Victor Lomuller(Codeplay), Liber Nevin(ANL), Hal Finkel (ANL)

Opens

No

Development update for past two weeks

• Added -fsycl-unnamed-lambda option has been added to make kernel naming optional.
• Windows support
  • Build passes. WIP on enabling CI configuration.
  • LIT tests enabling is in progress.
• Assertions
  • Fixing LIT tests is in progress.
  • We are going to enable assertions in pre-commit CI checks.
• Build with libcxx is fixed. OpenCL AS keywords are removed.
• New option to set SYCL version (big thanks to Ruyman!)
• Added FPGA specific command line options for AOT compilation mode.
• Fixed memory leaks in SYCL runtime related to cached program/kernel objects
• Added support for req_work_group_size
• Copy/fill methods are not blocking anymore (again).
• Added support for more advanced cases of hierarchical parallelism.
• Image support has been added
• Lower OpenCL version for Queue/sampler API.

Alexey: Andrew G, does the solution for generic pointer resolution proposed by Andrew Savonichev works for you?

Andrew Gozillon: haven't tried yet.

Ronan: another option to consider - do not generate address spaces in LLVM for Xilinx FPGA.

Alexey: address spaces can be useful for alias analysis. Isn't this important information to keep (even for FPGA)?

Ronan: it's a trade-off. Standard LLVM passes do not handle address spaces nicely today.