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config: add MMIO layout #339

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merged 2 commits into from
Feb 19, 2025
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gaojiaqi7
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The new configuration file contains the address and size of MMIO space and PCIE config space.

Closes #115

@gaojiaqi7 gaojiaqi7 force-pushed the 0211/add_mmio_layout_config branch 2 times, most recently from d72b805 to e82de11 Compare February 11, 2025 07:40
@jyao1
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jyao1 commented Feb 12, 2025

Can we add additional check for overlap between MMIO and physical RAM?

Just panic!() if this happens.

@gaojiaqi7 gaojiaqi7 force-pushed the 0211/add_mmio_layout_config branch 2 times, most recently from dadcedd to f0b6e32 Compare February 13, 2025 01:45
}

// Ensure that the MMIO64 range does not overlap with the MMIO32 space.
if config.mmio64_start > config.mmio32_start as u64
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@jyao1 jyao1 Feb 13, 2025

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Can we just simply make sure mmio64 > 4GB?

The rule is:

  1. mmio32 < 4GB
  2. mmio64 > 4GB
  3. PCIe should not overlap with them

u32::MAX as u64 + 1
};
if (end_of_ram > MMIO32_START as u64 && end_of_ram < (MMIO32_START + MMIO32_SIZE) as u64)
|| end_of_ram > MMIO64_START
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@jyao1 jyao1 Feb 13, 2025

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we need 2 end_of_ram value.

  1. top of low usable memory (< 4GB memory), not overlap with mmio32 range.
  2. top of up usable memory (> 4GB memory), not overlap with mmio64 range.

@gaojiaqi7 gaojiaqi7 force-pushed the 0211/add_mmio_layout_config branch from f0b6e32 to 0b1da35 Compare February 13, 2025 10:18
Signed-off-by: Jiaqi Gao <jiaqi.gao@intel.com>
The new configuration file contains the address and size of MMIO space and
PCIE config space.

Signed-off-by: Jiaqi Gao <jiaqi.gao@intel.com>
@gaojiaqi7 gaojiaqi7 force-pushed the 0211/add_mmio_layout_config branch from 0b1da35 to b10cdbc Compare February 17, 2025 07:39
@jyao1 jyao1 merged commit 9034e09 into intel:main Feb 19, 2025
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remove PCIE config access and hardcoded PCIE base
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