config: add MMIO layout

The new configuration file contains the address and size of MMIO space and
PCIE config space.

Signed-off-by: Jiaqi Gao <jiaqi.gao@intel.com>

config/mmio_layout.json

@@ -0,0 +1,8 @@
+{
+    "Mmio32Start": "0xC0000000",
+    "Mmio32Size": "0x20000000",
+    "PcieConfigBaseAddress": "0xE0000000",
+    "PcieConfigSize": "0x10000000",
+    "Mmio64Start": "0x100000000",
+    "Mmio64Size": "0x40000000"
+}

src/devices/pci/src/config.rs

@@ -6,11 +6,10 @@ use bitflags::bitflags;
 use core::convert::From;
 
 use crate::mmio::{alloc_mmio32, alloc_mmio64};
-use crate::{PciCommand, PciError, Result};
+use crate::{PciCommand, PciError, Result, PCI_EX_BAR_BASE_ADDRESS};
 
 pub const PCI_CONFIGURATION_ADDRESS_PORT: u16 = 0xCF8;
 pub const PCI_CONFIGURATION_DATA_PORT: u16 = 0xCFC;
-const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000u64;
 const PCI_MEM32_BASE_ADDRESS_MASK: u32 = 0xFFFF_FFF0;
 const PCI_MEM64_BASE_ADDRESS_MASK: u64 = 0xFFFF_FFFF_FFFF_FFF0;
 

src/devices/pci/src/layout.rs

@@ -0,0 +1,10 @@
+// Copyright (c) 2024 Intel Corporation
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+
+pub const MMIO32_START: u32 = 0xC0000000;
+pub const MMIO32_SIZE: u32 = 0x20000000;
+pub const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000;
+pub const PCI_EX_BAR_SIZE: u64 = 0x10000000;
+pub const MMIO64_START: u64 = 0x100000000;
+pub const MMIO64_SIZE: u64 = 0x40000000;

src/devices/pci/src/lib.rs

@@ -6,9 +6,11 @@
 
 mod config;
 mod consts;
+mod layout;
 mod mmio;
 pub use config::*;
 pub use consts::*;
+pub use layout::*;
 pub use mmio::*;
 
 #[cfg(feature = "fuzz")]

src/devices/pci/src/mmio.rs

@@ -5,14 +5,11 @@
 use lazy_static::lazy_static;
 use spin::Mutex;
 
-use crate::{PciError, Result};
-
-pub const MMIO32_START: u32 = 0xC000_0000;
-pub const MMIO32_SIZE: u32 = 0x2000_0000;
+use crate::{PciError, Result, MMIO32_SIZE, MMIO32_START, MMIO64_START};
 
 lazy_static! {
-    static ref MMIO32: Mutex<u32> = Mutex::new(0);
-    static ref MMIO64: Mutex<u64> = Mutex::new(0);
+    static ref MMIO32: Mutex<u32> = Mutex::new(MMIO32_START);
+    static ref MMIO64: Mutex<u64> = Mutex::new(MMIO64_START);
 }
 
 #[cfg(feature = "fuzz")]
@@ -21,15 +18,12 @@ lazy_static! {
 }
 
 pub fn init_mmio(end_of_ram: u64) {
-    *MMIO32.lock() = MMIO32_START;
-
-    let mmio64_start = if end_of_ram > u32::MAX as u64 {
-        end_of_ram
-    } else {
-        u32::MAX as u64 + 1
-    };
+    if end_of_ram > MMIO64_START {
+        panic!("Invalid MMIO64 configuration: MMIO64 space overlaps with the RAM space.");
+    }
 
-    *MMIO64.lock() = mmio64_start;
+    *MMIO32.lock() = MMIO32_START;
+    *MMIO64.lock() = MMIO64_START;
 }
 
 #[cfg(feature = "fuzz")]
@@ -45,6 +39,8 @@ pub fn alloc_mmio32(size: u32) -> Result<u32> {
 
 #[cfg(not(feature = "fuzz"))]
 pub fn alloc_mmio32(size: u32) -> Result<u32> {
+    use crate::MMIO32_SIZE;
+
     let cur = *MMIO32.lock();
     let addr = align_up(cur as u64, size as u64).ok_or(PciError::InvalidParameter)?;
 

src/migtd/src/driver/serial.rs

@@ -4,6 +4,7 @@
 
 use alloc::boxed::Box;
 use core::sync::atomic::AtomicBool;
+use pci::PCI_EX_BAR_BASE_ADDRESS;
 use td_payload::mm::shared::{alloc_shared_pages, free_shared_pages};
 use virtio_serial::*;
 
@@ -74,8 +75,6 @@ pub fn virtio_serial_device_init(end_of_ram: u64) {
 }
 
 pub fn pci_ex_bar_initialization() {
-    const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000u64;
-
     // PcdPciExpressBaseAddress TBD
     let pci_exbar_base = PCI_EX_BAR_BASE_ADDRESS;
 

src/migtd/src/driver/vsock.rs

@@ -95,7 +95,7 @@ pub fn virtio_vsock_device_init(end_of_ram: u64) {
 
 #[cfg(feature = "virtio-vsock")]
 pub fn pci_ex_bar_initialization() {
-    const PCI_EX_BAR_BASE_ADDRESS: u64 = 0xE0000000u64;
+    use pci::PCI_EX_BAR_BASE_ADDRESS;
 
     // PcdPciExpressBaseAddress TBD
     let pci_exbar_base = PCI_EX_BAR_BASE_ADDRESS;

xtask/Cargo.toml

@@ -10,3 +10,5 @@ clap = { version = "4.0", features = ["derive"] }
 xshell = "0.2"
 lazy_static = "1.4.0"
 anyhow = "1.0"
+serde_json = "1.0"
+serde = { version = "1.0", features = ["derive"] }

xtask/src/build.rs

@@ -11,6 +11,8 @@ use std::{
 };
 use xshell::{cmd, Shell};
 
+use crate::config;
+
 const MIGTD_DEFAULT_FEATURES: &str = "stack-guard,virtio-vsock";
 const MIGTD_KVM_FEATURES: &str = MIGTD_DEFAULT_FEATURES;
 const DEFAULT_IMAGE_NAME: &str = "migtd.bin";
@@ -27,6 +29,7 @@ lazy_static! {
     static ref DEFAULT_SHIM_LAYOUT: PathBuf = PROJECT_ROOT.join("config/shim_layout.json");
     static ref DEFAULT_IMAGE_LAYOUT: PathBuf = PROJECT_ROOT.join("config/image_layout.json");
     static ref DEFAULT_SERVTD_INFO: PathBuf = PROJECT_ROOT.join("config/servtd_info.json");
+    static ref MMIO_LAYOUT_SOURCE: PathBuf = PROJECT_ROOT.join("src/devices/pci/src/layout.rs");
 }
 
 #[derive(Clone, Args)]
@@ -66,6 +69,9 @@ pub(crate) struct BuildArgs {
     /// Log level control in migtd, default value is `off` for release and `info` for debug
     #[clap(short, long)]
     log_level: Option<LogLevel>,
+    /// MMIO space layout configuration for migtd
+    #[clap(long)]
+    mmio_config: Option<PathBuf>,
 }
 
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, ValueEnum)]
@@ -112,6 +118,7 @@ impl LogLevel {
 
 impl BuildArgs {
     pub fn build(&self) -> Result<PathBuf> {
+        self.create_mmio_config()?;
         let (reset_vector, shim) = self.build_shim()?;
         let migtd = self.build_migtd()?;
         let bin = self.build_final(reset_vector.as_path(), shim.as_path(), migtd.as_path())?;
@@ -165,6 +172,13 @@ impl BuildArgs {
         Ok(())
     }
 
+    fn create_mmio_config(&self) -> Result<()> {
+        if let Some(json_path) = &self.mmio_config {
+            config::generate_mmio_config(json_path, &MMIO_LAYOUT_SOURCE)?;
+        }
+        Ok(())
+    }
+
     fn build_migtd(&self) -> Result<PathBuf> {
         let sh = Shell::new()?;
         sh.set_var("CC_x86_64_unknown_none", "clang");