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Non-interleaved ring works fine, inherent issue with interleaved ring…
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… (injection of start pule). Abandon interleaving.
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@hpretl
hpretl committed Mar 20, 2024
1 parent 051fe03 commit 28c1eb2
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Showing 8 changed files with 16,175 additions and 13,965 deletions.
4 changes: 2 additions & 2 deletions sim/build.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,8 @@ MODULE=tdc_ring
[ -f $MODULE.mag ] && rm $MODULE.mag
[ -f $MODULE.pex.spice ] && rm $MODULE.pex.spice

# Copy user_config.tcl into proper folder
cp -f user_config.tcl ../src
# Copy correct user_config.tcl into src folder
cp -f user_config_$MODULE.tcl ../src/user_config.tcl

# Run OpenLane flow to build layout
flow.tcl -design ../src -tag foo -overwrite
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258 changes: 145 additions & 113 deletions sim/tb_tt06_tdc.sch
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Original file line number Diff line number Diff line change
Expand Up @@ -7,14 +7,14 @@ S {}
E {}
B 2 420 -1400 1820 -900 {flags=graph
y1=0
y2=2
y2=1.8
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=7e-07
x2=6e-07
divx=5
subdivx=1
xlabmag=1.0
Expand All @@ -26,31 +26,24 @@ unitx=1
logx=0
logy=0
digital=0
rainbow=1
rainbow=0




color="5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 4 5 6 7"
node="x1.w_dly_sig[21]
x1.w_dly_sig[20]
x1.w_dly_sig[19]
x1.w_dly_sig[18]
x1.w_dly_sig[17]
x1.w_dly_sig[16]
x1.w_dly_sig[15]
x1.w_dly_sig[14]
x1.w_dly_sig[13]
x1.w_dly_sig[12]
x1.w_dly_sig[11]
x1.w_dly_sig[10]
x1.w_dly_sig[9]
x1.w_dly_sig[8]
x1.w_dly_sig[7]
x1.w_dly_sig[6]
x1.w_dly_sig[5]
x1.w_dly_sig[4]
x1.w_dly_sig[3]
x1.w_dly_sig[2]
x1.w_dly_sig[1]"}
B 2 420 -1890 1820 -1460 {flags=graph


hilight_wave=6
color="7 8 6 9 10 11 12 13"
node="start
stop
dbg_dly[0]
dbg_dly[1]
dbg_dly[2]
dbg_dly[3]
dbg_dly[4]
dbg_dly[5]"}
B 2 420 -1980 1820 -1460 {flags=graph
y1=0
y2=2
ypos1=0
Expand All @@ -59,7 +52,7 @@ divy=5
subdivy=1
unity=1
x1=0
x2=7e-07
x2=6e-07
divx=5
subdivx=1
xlabmag=1.0
Expand All @@ -72,73 +65,112 @@ logx=0
logy=0
digital=1

color="7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7"
node="res[0]
res[1]
res[2]
res[3]
res[4]
res[5]
res[6]
res[7]
res[8]
res[9]
res[10]
res[11]
res[12]
res[13]
res[14]
res[15]
res[16]
res[17]
res[18]
res[19]
res[20]
res[21]
res[22]
res[23]
res[24]
res[25]
res[26]
res[27]
res[28]
res[29]
res[30]
res[31]
res[32]
res[33]
res[34]
res[35]
res[36]
res[37]
res[38]
res[39]
res[40]
res[41]
res[42]
res[43]
res[44]
res[45]
res[46]
res[47]
res[48]
res[49]
res[50]
res[51]
res[52]
res[53]
res[54]
res[55]
res[56]
res[57]
res[58]
res[59]
res[60]
res[61]
res[62]
res[63]
res[64]
res[65]"}

sim_type=tran
color="9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 7 7 7 7 7"
node="res_ctr[0]
res_ctr[1]
res_ctr[2]
res_ring[0]
res_ring[4]
res_ring[8]
res_ring[12]
res_ring[15]
res_ring[1]
res_ring[2]
res_ring[3]
res_ring[5]
res_ring[6]
res_ring[7]
res_ring[9]
res_ring[10]
res_ring[11]
res_ring[13]
res_ring[14]
dbg_dly[15]
dbg_dly[14]
dbg_dly[13]
dbg_dly[12]
dbg_dly[11]
dbg_dly[10]
dbg_dly[9]
dbg_dly[8]
dbg_dly[7]
dbg_dly[6]
dbg_dly[5]
dbg_dly[4]
dbg_dly[3]
dbg_dly[2]
dbg_dly[1]
dbg_dly[0]
stop
dbg_stop
dbg_ctr[0]
dbg_ctr[1]
dbg_ctr[2]"}
B 2 2040 -1360 2840 -960 {flags=graph
y1=0
y2=2
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=6e-07
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=dbg_dly[0]
color=13
dataset=-1
unitx=1
logx=0
logy=0
}
B 2 2040 -1800 2840 -1400 {flags=graph
y1=0
y2=2
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=6e-07
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=dbg_dly[1]
color=13
dataset=-1
unitx=1
logx=0
logy=0
}
B 2 2040 -2250 2840 -1850 {flags=graph
y1=0
y2=2
ypos1=0
ypos2=2
divy=5
subdivy=1
unity=1
x1=0
x2=6e-07
divx=5
subdivx=1
xlabmag=1.0
ylabmag=1.0
node=dbg_dly[2]
color=13
dataset=-1
unitx=1
logx=0
logy=0
}
N 340 -140 340 -120 {
lab=GND}
N 1330 -360 1330 -340 {
Expand All @@ -156,35 +188,35 @@ lab=stop}
N 1820 -280 1820 -240 {
lab=GND}
N 1510 -420 1580 -420 {
lab=res_ring[63:0]}
lab=res_ring[15:0]}
N 1820 -420 1820 -340 {
lab=res_ring[63:0]}
lab=res_ring[15:0]}
N 640 -420 1130 -420 {
lab=start}
N 640 -420 640 -380 {
lab=start}
N 1330 -600 1330 -560 {
lab=VDD}
N 1580 -420 1820 -420 {
lab=res_ring[63:0]}
lab=res_ring[15:0]}
N 1660 -280 1660 -240 {
lab=GND}
N 1510 -400 1660 -400 {
lab=res_ctr[7:0]}
lab=res_ctr[2:0]}
N 1660 -400 1660 -340 {
lab=res_ctr[7:0]}
lab=res_ctr[2:0]}
N 2140 -280 2140 -240 {
lab=GND}
N 1980 -280 1980 -240 {
lab=GND}
N 1510 -460 1980 -460 {
lab=dbg_dly[63:0]}
lab=dbg_dly[15:0]}
N 1980 -460 1980 -340 {
lab=dbg_dly[63:0]}
lab=dbg_dly[15:0]}
N 1510 -480 2140 -480 {
lab=dbg_ctr[7:0]}
lab=dbg_ctr[2:0]}
N 2140 -480 2140 -340 {
lab=dbg_ctr[7:0]}
lab=dbg_ctr[2:0]}
N 2280 -280 2280 -240 {
lab=GND}
N 1510 -500 2280 -500 {
Expand Down Expand Up @@ -225,10 +257,10 @@ write tb_tt06_tdc.raw
"}
C {devices/gnd.sym} 1330 -340 0 0 {name=l8 lab=GND}
C {devices/vdd.sym} 1330 -600 0 0 {name=l9 lab=VDD}
C {devices/vsource.sym} 640 -350 0 0 {name=VDAC value="0 pwl(0 0 500n 0 500.1n 1.8)"}
C {devices/vsource.sym} 640 -350 0 0 {name=VSTART value="0 pwl(0 0 500n 0 500.1n 1.8)"}
C {devices/gnd.sym} 640 -310 0 0 {name=l10 lab=GND}
C {devices/spice_probe.sym} 640 -420 0 0 {name=p1 attrs=""}
C {devices/vsource.sym} 840 -340 0 0 {name=VDAC1 value="0 pwl(0 0 508n 0 508.1n 1.8)"}
C {devices/vsource.sym} 840 -340 0 0 {name=VSTOP value="0 pwl(0 0 100n 1.8 200n 1.8 200.1n 0 508n 0 508.1n 1.8)"}
C {devices/gnd.sym} 840 -300 0 0 {name=l13 lab=GND}
C {devices/spice_probe.sym} 840 -400 0 0 {name=p2 attrs=""}
C {devices/lab_wire.sym} 900 -400 0 1 {name=l14 sig_type=std_logic lab=stop}
Expand All @@ -241,11 +273,11 @@ value="

"
spice_ignore=false}
C {devices/capa.sym} 1820 -310 0 0 {name=Cload1[63:0]
C {devices/capa.sym} 1820 -310 0 0 {name=Cload1[15:0]
m=1
value=10f}
C {devices/gnd.sym} 1820 -240 0 0 {name=l15 lab=GND}
C {devices/lab_wire.sym} 1540 -420 0 1 {name=l16 sig_type=std_logic lab=res_ring[63:0]}
C {devices/lab_wire.sym} 1540 -420 0 1 {name=l16 sig_type=std_logic lab=res_ring[15:0]}
C {devices/spice_probe.sym} 1820 -380 0 0 {name=p3 attrs=""}
C {devices/lab_wire.sym} 900 -420 0 1 {name=l4 sig_type=std_logic lab=start}
C {devices/launcher.sym} 300 -320 0 0 {name=h5
Expand All @@ -257,24 +289,24 @@ C {devices/vsource.sym} 340 -170 0 0 {name=VDAC2 value="0 pwl(0 0 100n 1.8)"}
C {devices/launcher.sym} 300 -380 0 0 {name=h2
descr="simulate"
tclcommand="xschem save; xschem netlist; xschem simulate"}
C {devices/capa.sym} 1660 -310 0 0 {name=Cload2[7:0]
C {devices/capa.sym} 1660 -310 0 0 {name=Cload2[2:0]
m=1
value=10f}
C {devices/gnd.sym} 1660 -240 0 0 {name=l5 lab=GND}
C {devices/lab_wire.sym} 1540 -400 0 1 {name=l6 sig_type=std_logic lab=res_ctr[7:0]}
C {devices/lab_wire.sym} 1540 -400 0 1 {name=l6 sig_type=std_logic lab=res_ctr[2:0]}
C {devices/spice_probe.sym} 1660 -380 0 0 {name=p5 attrs=""}
C {/foss/designs/sim/tdc_ring.sym} 1150 -380 0 0 {name=x1}
C {devices/capa.sym} 2140 -310 0 0 {name=Cload3[7:0]
C {devices/capa.sym} 2140 -310 0 0 {name=Cload3[2:0]
m=1
value=0.1f}
C {devices/gnd.sym} 2140 -240 0 0 {name=l7 lab=GND}
C {devices/capa.sym} 1980 -310 0 0 {name=Cload4[63:0]
C {devices/capa.sym} 1980 -310 0 0 {name=Cload4[15:0]
m=1
value=0.1f}
C {devices/gnd.sym} 1980 -240 0 0 {name=l11 lab=GND}
C {devices/lab_wire.sym} 1540 -460 0 1 {name=l12 sig_type=std_logic lab=dbg_dly[63:0]}
C {devices/lab_wire.sym} 1540 -460 0 1 {name=l12 sig_type=std_logic lab=dbg_dly[15:0]}
C {devices/spice_probe.sym} 1980 -380 0 0 {name=p6 attrs=""}
C {devices/lab_wire.sym} 1540 -480 0 1 {name=l17 sig_type=std_logic lab=dbg_ctr[7:0]}
C {devices/lab_wire.sym} 1540 -480 0 1 {name=l17 sig_type=std_logic lab=dbg_ctr[2:0]}
C {devices/spice_probe.sym} 2140 -380 0 0 {name=p7 attrs=""}
C {devices/capa.sym} 2280 -310 0 0 {name=Cload5
m=1
Expand Down
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