Intermediate state, not working correctly

iic-jku · Mar 17, 2024 · 051fe03 · 051fe03
1 parent 8437b59
commit 051fe03
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Showing 8 changed files with 16,563 additions and 46,697 deletions.
diff --git a/sim/build.sh b/sim/build.sh
@@ -2,8 +2,8 @@
 # Copyright (c) 2024 Harald Pretl, IIC@JKU
 # SPDX-License-Identifier: Apache-2.0
 
-MODULE=tt_um_hpretl_tt06_tdc_v1
-#MODULE=tdc
+#MODULE=tt_um_hpretl_tt06_tdc_v2
+MODULE=tdc_ring
 
 [ -f $MODULE.mag ] && rm $MODULE.mag
 [ -f $MODULE.pex.spice ] && rm $MODULE.pex.spice
@@ -26,4 +26,3 @@ rm $TMP
 
 # Remove "\"
 sed -i 's/\\//g' $MODULE.pex.spice
-
diff --git a/sim/tb_tt06_tdc.raw b/sim/tb_tt06_tdc.raw
diff --git a/sim/tb_tt06_tdc.sch b/sim/tb_tt06_tdc.sch
@@ -5,7 +5,7 @@ K {}
 V {}
 S {}
 E {}
-B 2 420 -1100 1820 -600 {flags=graph
+B 2 420 -1400 1820 -900 {flags=graph
 y1=0
 y2=2
 ypos1=0
@@ -50,7 +50,7 @@ x1.w_dly_sig[4]
 x1.w_dly_sig[3]
 x1.w_dly_sig[2]
 x1.w_dly_sig[1]"}
-B 2 420 -1590 1820 -1160 {flags=graph
+B 2 420 -1890 1820 -1460 {flags=graph
 y1=0
 y2=2
 ypos1=0
@@ -153,18 +153,50 @@ N 840 -400 1130 -400 {
 lab=stop}
 N 840 -400 840 -370 {
 lab=stop}
-N 1580 -280 1580 -240 {
+N 1820 -280 1820 -240 {
 lab=GND}
 N 1510 -420 1580 -420 {
-lab=res[65:0]}
-N 1580 -420 1580 -340 {
-lab=res[65:0]}
+lab=res_ring[63:0]}
+N 1820 -420 1820 -340 {
+lab=res_ring[63:0]}
 N 640 -420 1130 -420 {
 lab=start}
 N 640 -420 640 -380 {
 lab=start}
-N 1330 -500 1330 -460 {
+N 1330 -600 1330 -560 {
 lab=VDD}
+N 1580 -420 1820 -420 {
+lab=res_ring[63:0]}
+N 1660 -280 1660 -240 {
+lab=GND}
+N 1510 -400 1660 -400 {
+lab=res_ctr[7:0]}
+N 1660 -400 1660 -340 {
+lab=res_ctr[7:0]}
+N 2140 -280 2140 -240 {
+lab=GND}
+N 1980 -280 1980 -240 {
+lab=GND}
+N 1510 -460 1980 -460 {
+lab=dbg_dly[63:0]}
+N 1980 -460 1980 -340 {
+lab=dbg_dly[63:0]}
+N 1510 -480 2140 -480 {
+lab=dbg_ctr[7:0]}
+N 2140 -480 2140 -340 {
+lab=dbg_ctr[7:0]}
+N 2280 -280 2280 -240 {
+lab=GND}
+N 1510 -500 2280 -500 {
+lab=dbg_stop}
+N 2280 -500 2280 -340 {
+lab=dbg_stop}
+N 2380 -280 2380 -240 {
+lab=GND}
+N 1510 -520 2380 -520 {
+lab=dbg_start}
+N 2380 -520 2380 -340 {
+lab=dbg_start}
 C {devices/title.sym} 160 -30 0 0 {name=l1 author="Harald Pretl, IIC @ JKU"}
 C {devices/vdd.sym} 340 -220 0 0 {name=l2 lab=VDD}
 C {devices/gnd.sym} 340 -120 0 0 {name=l3 lab=GND}
@@ -175,29 +207,6 @@ value="
 * ngspice commands
 ****************
 
-.save v(x1.w_dly_sig[0])
-.save v(x1.w_dly_sig[1])
-.save v(x1.w_dly_sig[2])
-.save v(x1.w_dly_sig[3])
-.save v(x1.w_dly_sig[4])
-.save v(x1.w_dly_sig[5])
-.save v(x1.w_dly_sig[6])
-.save v(x1.w_dly_sig[7])
-.save v(x1.w_dly_sig[8])
-.save v(x1.w_dly_sig[9])
-.save v(x1.w_dly_sig[10])
-.save v(x1.w_dly_sig[11])
-.save v(x1.w_dly_sig[12])
-.save v(x1.w_dly_sig[13])
-.save v(x1.w_dly_sig[14])
-.save v(x1.w_dly_sig[15])
-.save v(x1.w_dly_sig[16])
-.save v(x1.w_dly_sig[17])
-.save v(x1.w_dly_sig[18])
-.save v(x1.w_dly_sig[19])
-.save v(x1.w_dly_sig[20])
-.save v(x1.w_dly_sig[21])
-
 ****************
 * Misc
 ****************
@@ -214,9 +223,8 @@ write tb_tt06_tdc.raw
 *exit
 .endc
 "}
-C {tdc.sym} 1150 -380 0 0 {name=x1}
 C {devices/gnd.sym} 1330 -340 0 0 {name=l8 lab=GND}
-C {devices/vdd.sym} 1330 -500 0 0 {name=l9 lab=VDD}
+C {devices/vdd.sym} 1330 -600 0 0 {name=l9 lab=VDD}
 C {devices/vsource.sym} 640 -350 0 0 {name=VDAC value="0 pwl(0 0 500n 0 500.1n 1.8)"}
 C {devices/gnd.sym} 640 -310 0 0 {name=l10 lab=GND}
 C {devices/spice_probe.sym} 640 -420 0 0 {name=p1 attrs=""}
@@ -233,12 +241,12 @@ value="
 
 "
 spice_ignore=false}
-C {devices/capa.sym} 1580 -310 0 0 {name=Cload[65:0]
+C {devices/capa.sym} 1820 -310 0 0 {name=Cload1[63:0]
 m=1
 value=10f}
-C {devices/gnd.sym} 1580 -240 0 0 {name=l15 lab=GND}
-C {devices/lab_wire.sym} 1540 -420 0 1 {name=l16 sig_type=std_logic lab=res[65:0]}
-C {devices/spice_probe.sym} 1580 -380 0 0 {name=p3 attrs=""}
+C {devices/gnd.sym} 1820 -240 0 0 {name=l15 lab=GND}
+C {devices/lab_wire.sym} 1540 -420 0 1 {name=l16 sig_type=std_logic lab=res_ring[63:0]}
+C {devices/spice_probe.sym} 1820 -380 0 0 {name=p3 attrs=""}
 C {devices/lab_wire.sym} 900 -420 0 1 {name=l4 sig_type=std_logic lab=start}
 C {devices/launcher.sym} 300 -320 0 0 {name=h5
 descr="load waves" 
@@ -249,3 +257,34 @@ C {devices/vsource.sym} 340 -170 0 0 {name=VDAC2 value="0 pwl(0 0 100n 1.8)"}
 C {devices/launcher.sym} 300 -380 0 0 {name=h2 
 descr="simulate" 
 tclcommand="xschem save; xschem netlist; xschem simulate"}
+C {devices/capa.sym} 1660 -310 0 0 {name=Cload2[7:0]
+m=1
+value=10f}
+C {devices/gnd.sym} 1660 -240 0 0 {name=l5 lab=GND}
+C {devices/lab_wire.sym} 1540 -400 0 1 {name=l6 sig_type=std_logic lab=res_ctr[7:0]}
+C {devices/spice_probe.sym} 1660 -380 0 0 {name=p5 attrs=""}
+C {/foss/designs/sim/tdc_ring.sym} 1150 -380 0 0 {name=x1}
+C {devices/capa.sym} 2140 -310 0 0 {name=Cload3[7:0]
+m=1
+value=0.1f}
+C {devices/gnd.sym} 2140 -240 0 0 {name=l7 lab=GND}
+C {devices/capa.sym} 1980 -310 0 0 {name=Cload4[63:0]
+m=1
+value=0.1f}
+C {devices/gnd.sym} 1980 -240 0 0 {name=l11 lab=GND}
+C {devices/lab_wire.sym} 1540 -460 0 1 {name=l12 sig_type=std_logic lab=dbg_dly[63:0]}
+C {devices/spice_probe.sym} 1980 -380 0 0 {name=p6 attrs=""}
+C {devices/lab_wire.sym} 1540 -480 0 1 {name=l17 sig_type=std_logic lab=dbg_ctr[7:0]}
+C {devices/spice_probe.sym} 2140 -380 0 0 {name=p7 attrs=""}
+C {devices/capa.sym} 2280 -310 0 0 {name=Cload5
+m=1
+value=0.1f}
+C {devices/gnd.sym} 2280 -240 0 0 {name=l18 lab=GND}
+C {devices/capa.sym} 2380 -310 0 0 {name=Cload1
+m=1
+value=0.1f}
+C {devices/gnd.sym} 2380 -240 0 0 {name=l19 lab=GND}
+C {devices/lab_wire.sym} 1540 -500 0 1 {name=l20 sig_type=std_logic lab=dbg_stop}
+C {devices/lab_wire.sym} 1540 -520 0 1 {name=l21 sig_type=std_logic lab=dbg_start}
+C {devices/spice_probe.sym} 2280 -380 0 0 {name=p8 attrs=""}
+C {devices/spice_probe.sym} 2380 -380 0 0 {name=p9 attrs=""}