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hpretl committed Mar 17, 2024
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This is a simple synthesized time-to-digital converter (TDC), consisting of a delay line and parallel capture FF. Depending on `__TDC_INTERLEAVED__` either a simple or an interleaved delay line is implemented.

In the TT 1x1 block size a 128-stage interleaved delay can be fitted.
In the TT 1x1 block size a 192-stage interleaved delay can be fitted.

## How to test

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