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[RISC-V] Fix Int32 to Unsigned overflow check #107024

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b112859
[RISC-V] Allowed CHECK_POSITIVE to have temporary register
Bajtazar Aug 26, 2024
f3fb8b3
[RISC-V] Fixed CHECK_POSITIVE in genIntCastOverflowCheck
Bajtazar Aug 26, 2024
9054a4e
[RISC-V] Improved J pseudoinstruction printing
Bajtazar Aug 26, 2024
1f7c669
[RISC-V] Added ret pseudoinstruction to disasm
Bajtazar Aug 26, 2024
4dcc555
[RISC-V] Fixed register type in disasm
Bajtazar Aug 26, 2024
144629f
[RISC-V] Fixed ins_Load
Bajtazar Aug 27, 2024
0a595fb
[RISC-V] Formatted code
Bajtazar Aug 27, 2024
87105a9
Merge branch 'main' into riscv-positive-int-overflow-fix
Bajtazar Aug 27, 2024
c68c1cd
[RISC-V] Fixed format bug
Bajtazar Aug 27, 2024
9b268e9
Merge branch 'riscv-positive-int-overflow-fix' of github.com:Bajtazar…
Bajtazar Aug 27, 2024
bd678ee
Revert "[RISC-V] Fixed ins_Load"
Bajtazar Aug 27, 2024
4bef7fb
[RISC-V] Fixed comment in codegenlinear
Bajtazar Aug 27, 2024
eea0be5
[RISC-V] Fixed sextw attribute type
Bajtazar Aug 27, 2024
cdb7924
[RISC-V] Simplified casts logic
Bajtazar Aug 27, 2024
1b4907e
[RISC-V] Improved CHECK_SMALL_INT_RANGE casts
Bajtazar Aug 27, 2024
d063b64
[RISC-V] Optimized check int range
Bajtazar Aug 27, 2024
4dffd5f
[RISC-V] Fixes in codegenriscv64
Bajtazar Aug 27, 2024
74868f2
[RISC-V] Removed unused comment
Bajtazar Aug 27, 2024
bc09d23
[RISC-V] Fixed long/ulong casts
Bajtazar Aug 27, 2024
44e7411
[RISC-V] Added some comments
Bajtazar Aug 27, 2024
75d7405
[RISC-V] Fixes in CHECK_SMALL_INT_RANGE
Bajtazar Aug 28, 2024
eba998a
[RISC-V] More bugfixes in int casts
Bajtazar Aug 28, 2024
5fdc67f
[RISC-V] Generalized CHECK_SMALL_INT_RANGE a little bit
Bajtazar Aug 29, 2024
209a8b1
Merge branch 'main' into riscv-positive-int-overflow-fix
Bajtazar Sep 3, 2024
5db2482
[RISC-V] Fixed typo
Bajtazar Sep 3, 2024
97c951c
Merge branch 'main' into riscv-positive-int-overflow-fix
Bajtazar Sep 3, 2024
daa73aa
Merge branch 'main' into riscv-positive-int-overflow-fix
Bajtazar Sep 4, 2024
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4 changes: 2 additions & 2 deletions src/coreclr/jit/codegenlinear.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -848,7 +848,7 @@ void CodeGen::genCodeForBBlist()
}
compiler->compCurBB = nullptr;
#endif // DEBUG
} //------------------ END-FOR each block of the method -------------------
} //------------------ END-FOR each block of the method -------------------

#if defined(FEATURE_EH_WINDOWS_X86)
// If this is a synchronized method on x86, and we generated all the code without
Expand Down Expand Up @@ -2526,7 +2526,7 @@ CodeGen::GenIntCastDesc::GenIntCastDesc(GenTreeCast* cast)
break;

#ifdef TARGET_64BIT
case ZERO_EXTEND_INT: // ubyte/ushort/int -> long.
case ZERO_EXTEND_INT: // ubyte/ushort/uint -> long.
assert(varTypeIsUnsigned(srcLoadType) || (srcLoadType == TYP_INT));
m_extendKind = varTypeIsSmall(srcLoadType) ? LOAD_ZERO_EXTEND_SMALL_INT : LOAD_ZERO_EXTEND_INT;
m_extendSrcSize = genTypeSize(srcLoadType);
Expand Down
15 changes: 7 additions & 8 deletions src/coreclr/jit/codegenriscv64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -6227,17 +6227,19 @@ void CodeGen::genJmpPlaceVarArgs()
//
void CodeGen::genIntCastOverflowCheck(GenTreeCast* cast, const GenIntCastDesc& desc, regNumber reg)
{
const regNumber tempReg = internalRegisters.GetSingle(cast);

switch (desc.CheckKind())
{
case GenIntCastDesc::CHECK_POSITIVE:
{
genJumpToThrowHlpBlk_la(SCK_OVERFLOW, INS_blt, reg, nullptr, REG_R0);
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@Bajtazar Bajtazar Aug 27, 2024

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If I am correct this piece of code is invoked during uint -> int conversion. That would mean that if the uint > 0x7f'ff'ff'ff the old comparation wouldn't work since it wouldn't be classified as an overflow

GetEmitter()->emitIns_R_R(INS_sext_w, EA_8BYTE, tempReg, reg);
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genJumpToThrowHlpBlk_la(SCK_OVERFLOW, INS_blt, tempReg, nullptr, REG_R0);
}
break;

case GenIntCastDesc::CHECK_UINT_RANGE:
{
regNumber tempReg = internalRegisters.GetSingle(cast);
// We need to check if the value is not greater than 0xFFFFFFFF
// if the upper 32 bits are zero.
ssize_t imm = -1;
Expand All @@ -6251,7 +6253,6 @@ void CodeGen::genIntCastOverflowCheck(GenTreeCast* cast, const GenIntCastDesc& d

case GenIntCastDesc::CHECK_POSITIVE_INT_RANGE:
{
regNumber tempReg = internalRegisters.GetSingle(cast);
// We need to check if the value is not greater than 0x7FFFFFFF
// if the upper 33 bits are zero.
// instGen_Set_Reg_To_Imm(EA_8BYTE, tempReg, 0xFFFFFFFF80000000LL);
Expand All @@ -6267,7 +6268,6 @@ void CodeGen::genIntCastOverflowCheck(GenTreeCast* cast, const GenIntCastDesc& d

case GenIntCastDesc::CHECK_INT_RANGE:
{
const regNumber tempReg = internalRegisters.GetSingle(cast);
assert(tempReg != reg);
GetEmitter()->emitLoadImmediate(EA_8BYTE, tempReg, INT32_MAX);
genJumpToThrowHlpBlk_la(SCK_OVERFLOW, INS_blt, tempReg, nullptr, reg);
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Expand All @@ -6280,10 +6280,9 @@ void CodeGen::genIntCastOverflowCheck(GenTreeCast* cast, const GenIntCastDesc& d
default:
{
assert(desc.CheckKind() == GenIntCastDesc::CHECK_SMALL_INT_RANGE);
const int castMaxValue = desc.CheckSmallIntMax();
const int castMinValue = desc.CheckSmallIntMin();
const regNumber tempReg = internalRegisters.GetSingle(cast);
instruction ins;
const int castMaxValue = desc.CheckSmallIntMax();
const int castMinValue = desc.CheckSmallIntMin();
instruction ins;

if (castMaxValue > 2047)
{
Expand Down
26 changes: 21 additions & 5 deletions src/coreclr/jit/emitriscv64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3914,14 +3914,21 @@ void emitter::emitDispInsName(
}
case 0x67:
{
const char* rs1 = RegNames[(code >> 15) & 0x1f];
const char* rd = RegNames[(code >> 7) & 0x1f];
int offset = ((code >> 20) & 0xfff);
const unsigned rs1 = (code >> 15) & 0x1f;
const unsigned rd = (code >> 7) & 0x1f;
int offset = ((code >> 20) & 0xfff);
if (offset & 0x800)
{
offset |= 0xfffff000;
}
printf("jalr %s, %d(%s)", rd, offset, rs1);

if ((rs1 == REG_RA) && (rd == REG_ZERO))
{
printf("ret");
return;
}

printf("jalr %s, %d(%s)", RegNames[rd], offset, RegNames[rs1]);
CORINFO_METHOD_HANDLE handle = (CORINFO_METHOD_HANDLE)id->idDebugOnlyInfo()->idMemCookie;
// Target for ret call is unclear, e.g.:
// jalr zero, 0(ra)
Expand All @@ -3946,7 +3953,16 @@ void emitter::emitDispInsName(
}
if (rd == REG_ZERO)
{
printf("j %d", offset);
printf("j ");

if (id->idIsBound())
{
emitPrintLabel(id->idAddr()->iiaIGlabel);
}
else
{
printf("pc%+d instructions", offset >> 2);
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}
}
else
{
Expand Down
7 changes: 5 additions & 2 deletions src/coreclr/jit/instr.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1861,9 +1861,12 @@ instruction CodeGenInterface::ins_Load(var_types srcType, bool aligned /*=false*
else
ins = INS_lh;
}
else if (TYP_INT == srcType)
else if (varTypeIsInt(srcType))
{
ins = INS_lw;
if (varTypeIsUnsigned(srcType))
ins = INS_lwu;
else
ins = INS_lw;
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}
else
{
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/lsrariscv64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1284,7 +1284,7 @@ int LinearScan::BuildBlockStore(GenTreeBlk* blkNode)
int LinearScan::BuildCast(GenTreeCast* cast)
{
enum CodeGen::GenIntCastDesc::CheckKind kind = CodeGen::GenIntCastDesc(cast).CheckKind();
if ((kind != CodeGen::GenIntCastDesc::CHECK_NONE) && (kind != CodeGen::GenIntCastDesc::CHECK_POSITIVE))
if ((kind != CodeGen::GenIntCastDesc::CHECK_NONE))
{
buildInternalIntRegisterDefForNode(cast);
}
Expand Down
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