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diogodanielsoaresferreira/FPGAMastermind

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Apresentação
Apresentação
 
 
db
db
 
 
output_files
output_files
 
 
simulation/modelsim
simulation/modelsim
 
 
Anexo 1 - Diagrama de Blocos.jpeg
Anexo 1 - Diagrama de Blocos.jpeg
 
 
Anexo 2 - RandomNumber (Máquina de Estados).jpg
Anexo 2 - RandomNumber (Máquina de Estados).jpg
 
 
Anexo 3 - CheckEnd (Máquina de Estados).jpg
Anexo 3 - CheckEnd (Máquina de Estados).jpg
 
 
Anexo 4 - Compare (Máquina de Estados).jpg
Anexo 4 - Compare (Máquina de Estados).jpg
 
 
Bin7SegDecoder.vhd
Bin7SegDecoder.vhd
 
 
Bin7SegDecoder.vhd.bak
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Blink.vhd
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Demultiplexer.vhd
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FreqDivider.vhd
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LSD_REL.pdf
LSD_REL.pdf
 
 
LSD_REL.tex
LSD_REL.tex
 
 
LSD_REL_FINAL.pdf
LSD_REL_FINAL.pdf
 
 
LSD_REL_FINAL.tex
LSD_REL_FINAL.tex
 
 
Maquinas es Estados.pptx
Maquinas es Estados.pptx
 
 
MasterMind.vhd
MasterMind.vhd
 
 
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MasterMind.vhd.bak
 
 
MasterMind_Str.vhd
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MasterMind_final.qpf
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MasterMind_final.qsf
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MasterMind_final.qsf.bak
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MasterMind_final_nativelink_simulation.rpt
MasterMind_final_nativelink_simulation.rpt
 
 
README.md
README.md
 
 
RandomNumber.vhd
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checkEnd.vhd
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counteranddem_tb.vhd
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ua_logo.png
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FPGA Mastermind

Project presented on Digital Systems Labs course (Univerisdade de Aveiro), 2015.

The application is done using Altera Quartus framework, and programs the FPGA with the mastermind game.

Diogo Ferreira
Eduardo Silva

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Program the FPGA with mastermind game

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fpga vhdl altera mastermind mastermind-board-game digital-systems quartus universidade-de-aveiro

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