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[RISCV] [linux-6.6.y] add xuantie erreta #418

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merged 6 commits into from
Sep 16, 2024
Merged

[RISCV] [linux-6.6.y] add xuantie erreta #418

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1220f73
riscv: errata: Replace thead cache clean with flush
xingxg2022 Jan 22, 2024
2e3f73b
riscv: errata: cmo: add CMO macro variant with both VA and PA
Icenowy Jan 4, 2023
c182b4d
riscv: use VA+PA variant of CMO macros for DMA synchorization
Icenowy Jan 4, 2023
e2f9973
riscv: use VA+PA variant of CMO macros for DMA page preparation
Icenowy Jan 4, 2023
94ca55e
riscv: errata: thead: Make cache clean to flush
xingxg2022 Oct 19, 2023
dfbaf89
riscv: changing T-Head PBMT attributes
Icenowy Feb 24, 2023
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32 changes: 31 additions & 1 deletion arch/riscv/include/asm/errata_list.h
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Original file line number Diff line number Diff line change
Expand Up @@ -128,9 +128,12 @@ asm volatile(ALTERNATIVE( \
* 0000000 11001 00000 000 00000 0001011
*/
#define THEAD_inval_A0 ".long 0x0265000b"
#define THEAD_clean_A0 ".long 0x0255000b"
#define THEAD_clean_A0 ".long 0x0275000b"
#define THEAD_flush_A0 ".long 0x0275000b"
#define THEAD_SYNC_S ".long 0x0190000b"
#define THEAD_inval_PA_A0 ".long 0x02a5000b"
#define THEAD_clean_PA_A0 ".long 0x02b5000b"
#define THEAD_flush_PA_A0 ".long 0x02b5000b"

#define ALT_CMO_OP(_op, _start, _size, _cachesize) \
asm volatile(ALTERNATIVE_2( \
Expand All @@ -157,6 +160,33 @@ asm volatile(ALTERNATIVE_2( \
"r"((unsigned long)(_start) + (_size)) \
: "a0")

#define ALT_CMO_OP_VPA(_op, _vaddr, _paddr, _size, _cachesize) \
asm volatile(ALTERNATIVE_2( \
__nops(6), \
"mv a0, %1\n\t" \
"j 2f\n\t" \
"3:\n\t" \
"cbo." __stringify(_op) " (a0)\n\t" \
"add a0, a0, %0\n\t" \
"2:\n\t" \
"bltu a0, %2, 3b\n\t" \
"nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \
"mv a0, %3\n\t" \
"j 2f\n\t" \
"3:\n\t" \
THEAD_##_op##_PA_A0 "\n\t" \
"add a0, a0, %0\n\t" \
"2:\n\t" \
"bltu a0, %4, 3b\n\t" \
THEAD_SYNC_S, THEAD_VENDOR_ID, \
ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \
: : "r"(_cachesize), \
"r"((unsigned long)(_vaddr) & ~((_cachesize) - 1UL)), \
"r"((unsigned long)(_vaddr) + (_size)), \
"r"((unsigned long)(_paddr) & ~((_cachesize) - 1UL)), \
"r"((unsigned long)(_paddr) + (_size)) \
: "a0")

#define THEAD_C9XX_RV_IRQ_PMU 17
#define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5

Expand Down
8 changes: 4 additions & 4 deletions arch/riscv/include/asm/pgtable-64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -127,13 +127,13 @@ enum napot_cont_order {
/*
* [63:59] T-Head Memory Type definitions:
*
* 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
* 00010 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
* 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
* 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
* 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
*/
#define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
#define _PAGE_NOCACHE_THEAD 0UL
#define _PAGE_IO_THEAD (1UL << 63)
#define _PAGE_NOCACHE_THEAD ((1UL << 61) | (1UL << 60))
#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60))
#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))

static inline u64 riscv_page_mtmask(void)
Expand Down
9 changes: 5 additions & 4 deletions arch/riscv/mm/dma-noncoherent.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
return;
}
#endif
ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
ALT_CMO_OP_VPA(clean, vaddr, paddr, size, riscv_cbom_block_size);
}

static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
Expand All @@ -39,7 +39,7 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
}
#endif

ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
ALT_CMO_OP_VPA(inval, vaddr, paddr, size, riscv_cbom_block_size);
}

static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
Expand All @@ -53,7 +53,7 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
}
#endif

ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
ALT_CMO_OP_VPA(flush, vaddr, paddr, size, riscv_cbom_block_size);
}

static inline bool arch_sync_dma_clean_before_fromdevice(void)
Expand Down Expand Up @@ -117,6 +117,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
void arch_dma_prep_coherent(struct page *page, size_t size)
{
void *flush_addr = page_address(page);
phys_addr_t paddr = PFN_PHYS(page_to_pfn(page));

#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
if (unlikely(noncoherent_cache_ops.wback_inv)) {
Expand All @@ -125,7 +126,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
}
#endif

ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
ALT_CMO_OP_VPA(flush, flush_addr, paddr, size, riscv_cbom_block_size);
}

void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
Expand Down
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