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[RISCV] [linux-6.6.y] add xuantie erreta #418

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RevySR
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@RevySR RevySR commented Sep 13, 2024

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xingxg2022 and others added 6 commits September 13, 2024 23:58
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
The standardized Zicbom extension supports only VA, however there's some
vendor extensions (e.g. XtheadCmo) that can handle cache management
operations on PA directly, bypassing the TLB lookup.

Add a CMO alternatives macro variant that come with both VA and PA
supplied, and the code can be patched to use either the VA or the PA at
runtime. In this case the codepath is now patched to use VA for Zicbom
and PA for XtheadCmo.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Guo Ren <guoren@kernel.org>
DMA synchorization is done on PA and the VA is calculated from the PA.

Use the alternative macro variant that takes both VA and PA as
parameters, thus in case the ISA extension used support PA directly, the
overhead for re-converting VA to PA can be omitted.

Suggested-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Reviewed-by: Guo Ren <guoren@kernel.org>
When doing DMA page preparation, both the VA and the PA are easily
accessible from struct page.

Use the alternative macro variant that takes both VA and PA as
parameters, thus in case the ISA extension used support PA directly, the
overhead for re-converting VA to PA can be omitted.

Suggested-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Originall the T-Head PBMT implementation in the kernel is intended for
D1, thus the Sharable bit is not set. In addition, the Bufferable bit
is not set for writecombine situation.

Set these bits in the T-Head PBMT attributes definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
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deepin pr auto review

关键摘要:

  • arch/riscv/include/asm/errata_list.h中,#define THEAD_clean_A0的值从0x0255000b更改为0x0275000b,需要确认这是否是有意为之,因为这可能会影响其他使用该宏的地方。
  • arch/riscv/include/asm/pgtable-64.h中,#define _PAGE_NOCACHE_THEAD#define _PAGE_IO_THEAD的值更改可能反映了不同的内存类型定义,需要检查这些更改是否与系统架构和需求相符。
  • arch/riscv/mm/dma-noncoherent.c中,ALT_CMO_OP_VPA宏的使用替代了原有的ALT_CMO_OP宏,这可能是为了支持不同的内存操作类型。需要验证这种替换是否正确,并且是否有相应的测试来验证这一更改不会引入新的错误。

是否建议立即修改:

  • 是,需要确保这些更改是基于准确的需求分析和测试。如果这些更改没有经过充分验证,可能会引入错误或兼容性问题。

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opsiff commented Sep 16, 2024

00010 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable 注释需要修改
和#define _PAGE_NOCACHE_THEAD ((1UL << 61) | (1UL << 60))宏定义一致

@opsiff opsiff merged commit fc5dc34 into deepin-community:linux-6.6.y Sep 16, 2024
4 of 5 checks passed
@opsiff opsiff changed the title [RISCV] add xuantie erreta [RISCV] [linux-6.6.y] add xuantie erreta Sep 16, 2024
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5 participants