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[RISCV] [linux-6.6.y] add xuantie erreta #418
[RISCV] [linux-6.6.y] add xuantie erreta #418
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Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
The standardized Zicbom extension supports only VA, however there's some vendor extensions (e.g. XtheadCmo) that can handle cache management operations on PA directly, bypassing the TLB lookup. Add a CMO alternatives macro variant that come with both VA and PA supplied, and the code can be patched to use either the VA or the PA at runtime. In this case the codepath is now patched to use VA for Zicbom and PA for XtheadCmo. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Guo Ren <guoren@kernel.org>
DMA synchorization is done on PA and the VA is calculated from the PA. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Guo Ren <guoren@kernel.org>
When doing DMA page preparation, both the VA and the PA are easily accessible from struct page. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren <guoren@kernel.org> Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Originall the T-Head PBMT implementation in the kernel is intended for D1, thus the Sharable bit is not set. In addition, the Bufferable bit is not set for writecombine situation. Set these bits in the T-Head PBMT attributes definition. Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
deepin pr auto review关键摘要:
是否建议立即修改:
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[APPROVALNOTIFIER] This PR is NOT APPROVED This pull-request has been approved by: The full list of commands accepted by this bot can be found here.
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00010 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable 注释需要修改 |
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