FROMPULL: soc: arm: npcx: fix clock reference of APB4/FIU1 buses

This CL fixes the clock reference of APB4/FIU1 buses by introducing new Kconfig options. Signed-off-by: Mulin Chao <mlchao@nuvoton.com> (cherry picked from commit 76b0aab) Manaul cherry-pick of: zephyrproject-rtos/zephyr#65204 This needs to be merged with a reland of chromium:5016743 to avoid a merge conflict. BUG=b:310935269 TEST=zmake build -a. Verify UART on Brya (npcx9 device) Change-Id: I66272f29025fd893e31fd954e28518f5b7b9d7b9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5037870 Tested-by: Keith Short <keithshort@chromium.org> Reviewed-by: Al Semjonovs <asemjonovs@google.com> Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
coreboot · Nov 16, 2023 · 960f724 · 960f724
1 parent a8324c6
commit 960f724
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Showing 4 changed files with 28 additions and 18 deletions.
diff --git a/drivers/clock_control/Kconfig.npcx b/drivers/clock_control/Kconfig.npcx
@@ -18,3 +18,15 @@ config CLOCK_CONTROL_NPCX_EXTERNAL_SRC
 	  is generated by the on-chip Crystal Oscillator (XTOSC).
 	  This includes an on-chip oscillator, to which an external crystal
 	  and the related passive components are connected.
+
+config CLOCK_CONTROL_NPCX_SUPP_APB4
+	bool "Indicates that the clock controller supports APB4 bus"
+	default y if !SOC_SERIES_NPCX7
+	help
+	  Selected if NPCX series supports APB4 bus.
+
+config CLOCK_CONTROL_NPCX_SUPP_FIU1
+	bool "Indicates that the clock controller supports FIU1 bus"
+	default y if SOC_SERIES_NPCX4
+	help
+	  Selected if NPCX series supports FIU1 bus.
diff --git a/soc/arm/nuvoton_npcx/common/soc_clock.h b/soc/arm/nuvoton_npcx/common/soc_clock.h
@@ -42,6 +42,14 @@ struct npcx_clk_cfg {
 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
 /* APB3 clock divider */
 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
+/* APB4 clock divider if supported */
+#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
+#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_APB4) /* Supported in NPCX9 and later series */
+#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
+#else
+#error "APB4 clock divider is not supported but defined in pcc node!"
+#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_APB4 */
+#endif
 
 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
 #define NPCX_PWDWN_CTL_ITEMS_INIT(node, prop, idx) DT_PROP_BY_IDX(node, prop, idx),
@@ -89,6 +97,14 @@ struct npcx_clk_cfg {
 #define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
 #endif
 
+#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
+#else
+#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
+#endif
+#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
+
 /* Get APB clock freq */
 #define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
 

diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.h b/soc/arm/nuvoton_npcx/npcx4/soc.h
@@ -58,16 +58,4 @@
 #include <soc_pins.h>
 #include <soc_power.h>
 
-/* NPCX4 Clock definitions */
-#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
-/* APB4 clock divider if supported */
-#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
-#endif
-
-#if (CORE_CLK > (MAX_OFMCLK / 2))
-#define FIU1DIV_VAL 1 /* If CORE_CLK > MAX_OFMCLK / 2, FIU1_CLK = CORE_CLK/2 */
-#else
-#define FIU1DIV_VAL 0 /* Else, FIU1_CLK = CORE_CLK */
-#endif
-
 #endif /* _NUVOTON_NPCX_SOC_H_ */
diff --git a/soc/arm/nuvoton_npcx/npcx9/soc.h b/soc/arm/nuvoton_npcx/npcx9/soc.h
@@ -56,10 +56,4 @@
 #include <soc_pins.h>
 #include <soc_power.h>
 
-/* NPCX9 Clock definitions */
-#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
-/* APB4 clock divider if supported */
-#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
-#endif
-
 #endif /* _NUVOTON_NPCX_SOC_H_ */