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Surelog parses more attributes for nets, modules, while at it support formal at… #5955

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Surelog parses more attributes for nets, modules, while at it support formal at…

Surelog parses more attributes for nets, modules, while at it support formal at… #5955

Re-run triggered October 4, 2024 05:56
@kamilrakoczykamilrakoczy
#2605
alaindargelas:attr_support
Status Failure
Total duration 14m 45s
Artifacts 48

main.yml

on: pull_request
Matrix: build-binaries
Build tools
10m 47s
Build tools
Emit Workflow Info
0s
Emit Workflow Info
Style check
2m 0s
Style check
Verify README Correctness (Installation From Sources)
40m 38s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 28s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
11m 15s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
29m 4s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
56m 59s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 32s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
14m 25s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
38m 30s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
34m 3s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 29s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 30s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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Annotations

1 error and 7 warnings
Formal Verification Tests / yosys
Process completed with exit code 1.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Formal Verification Tests / sv2v
No files were found with the provided path: sv2v_formal_verification_logs.tar. No artifacts will be uploaded.
Formal Verification Tests / simple
No files were found with the provided path: simple_formal_verification_logs.tar. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Formal Verification Tests / yosys
No files were found with the provided path: yosys_formal_verification_logs.tar. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
plots_formal_verification_yosys
98.4 KB
plots_ibex_synth_f4pga
80.4 KB
top_artya7.bit
121 KB