Zk(Zbk, Zkn, Zks)/Zb: Scalar Cryptography/Bitmanip Extension

.github/workflows/mill-ci.yml

@@ -65,7 +65,7 @@ jobs:
     runs-on: [self-hosted, linux]
     strategy:
       matrix:
-        config: ["DefaultRV32Config,32,RV32IMAC", "DefaultConfig,64,RV64IMAC"]
+        config: ["DefaultRV32Config,32,RV32IMAC", "DefaultConfig,64,RV64IMAC", "BitmanipCryptoConfig,64,RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh", "BitmanipCrypto32Config,32,RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"]
     steps:
       - uses: actions/checkout@v2
         with:

build.sc

@@ -62,6 +62,8 @@ object emulator extends mill.Cross[Emulator](
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitmanipCryptoConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitmanipCrypto32Config"),
   // Misc
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultSmallConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DualBankConfig"),
@@ -338,6 +340,9 @@ object `runnable-arch-test` extends mill.Cross[ArchTest](
   // zicsr is disabled due to ebreak issue
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "64", "RV64IMAC"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "32", "RV32IMAC"),
+
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitmanipCryptoConfig", "64", "RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitmanipCrypto32Config", "32", "RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
 )
 class ArchTest(top: String, config: String, xlen: String, isa: String) extends Module {
   def ispecString = T {

scripts/arch-test/emulator/riscof_emulator.py

@@ -107,6 +107,30 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += 'd'
       if "C" in ispec["ISA"]:
           self.isa += 'c'
+      if "Zba" in ispec["ISA"]:
+          self.isa += '_Zba'
+      if "Zbb" in ispec["ISA"]:
+          self.isa += '_Zbb'
+      if "Zbc" in ispec["ISA"]:
+          self.isa += '_Zbc'
+      if "Zbkb" in ispec["ISA"]:
+          self.isa += '_Zbkb'
+      if "Zbkc" in ispec["ISA"]:
+          self.isa += '_Zbkc'
+      if "Zbkx" in ispec["ISA"]:
+          self.isa += '_Zbkx'
+      if "Zbs" in ispec["ISA"]:
+          self.isa += '_Zbs'
+      if "Zknd" in ispec["ISA"]:
+          self.isa += '_Zknd'
+      if "Zkne" in ispec["ISA"]:
+          self.isa += '_Zkne'
+      if "Zknh" in ispec["ISA"]:
+          self.isa += '_Zknh'
+      if "Zksed" in ispec["ISA"]:
+          self.isa += '_Zksed'
+      if "Zksh" in ispec["ISA"]:
+          self.isa += '_Zksh'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately
@@ -153,7 +177,7 @@ def runTests(self, testList):
 
           # substitute all variables in the compile command that we created in the initialize
           # function
-          cmd = self.compile_cmd.format(testentry['isa'].lower(), test, elf, compile_macros)
+          cmd = self.compile_cmd.format(self.isa.lower(), test, elf, compile_macros)
 
 	  # if the user wants to disable running the tests and only compile the tests, then
 	  # the "else" clause is executed below assigning the sim command to simple no action

scripts/arch-test/spike/riscof_spike.py

@@ -107,6 +107,30 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += 'd'
       if "C" in ispec["ISA"]:
           self.isa += 'c'
+      if "Zba" in ispec["ISA"]:
+          self.isa += '_Zba'
+      if "Zbb" in ispec["ISA"]:
+          self.isa += '_Zbb'
+      if "Zbc" in ispec["ISA"]:
+          self.isa += '_Zbc'
+      if "Zbkb" in ispec["ISA"]:
+          self.isa += '_Zbkb'
+      if "Zbkc" in ispec["ISA"]:
+          self.isa += '_Zbkc'
+      if "Zbkx" in ispec["ISA"]:
+          self.isa += '_Zbkx'
+      if "Zbs" in ispec["ISA"]:
+          self.isa += '_Zbs'
+      if "Zknd" in ispec["ISA"]:
+          self.isa += '_Zknd'
+      if "Zkne" in ispec["ISA"]:
+          self.isa += '_Zkne'
+      if "Zknh" in ispec["ISA"]:
+          self.isa += '_Zknh'
+      if "Zksed" in ispec["ISA"]:
+          self.isa += '_Zksed'
+      if "Zksh" in ispec["ISA"]:
+          self.isa += '_Zksh'
 
       #TODO: The following assumes you are using the riscv-gcc toolchain. If
       #      not please change appropriately
@@ -153,7 +177,7 @@ def runTests(self, testList):
 
           # substitute all variables in the compile command that we created in the initialize
           # function
-          cmd = self.compile_cmd.format(testentry['isa'].lower(), test, elf, compile_macros)
+          cmd = self.compile_cmd.format(self.isa.lower(), test, elf, compile_macros)
 
 	  # if the user wants to disable running the tests and only compile the tests, then
 	  # the "else" clause is executed below assigning the sim command to simple no action

src/main/scala/rocket/ABLU.scala

@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package freechips.rocketchip.rocket
+
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.tile.CoreModule
+
+object ABLU extends ALUFN
+{
+  override val SZ_ALU_FN = 39
+  override def FN_X        = BitPat("b??_???_????_????_????__????__??_????_????_????_????")
+  override def FN_ADD      = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SL       = "b00_000_0000_1100_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
+  override def FN_SEQ      = "b00_100_0000_0000_0000__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
+  override def FN_SNE      = "b00_110_0000_0000_0000__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
+  override def FN_XOR      = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W)
+  override def FN_SR       = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
+  override def FN_OR       = "b00_000_0000_0000_0000__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W)
+  override def FN_AND      = "b00_000_0000_0000_0000__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W)
+  override def FN_SUB      = "b00_000_0000_0000_0011__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SRA      = "b00_000_0000_0001_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
+  override def FN_SLT      = "b00_000_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
+  override def FN_SGE      = "b00_010_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
+  override def FN_SLTU     = "b00_001_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
+  override def FN_SGEU     = "b00_011_0000_0000_0011__0001__00_0000_0000_0100_0000".U(SZ_ALU_FN.W)
+
+  // from Zb
+  // Zba: UW is encoded here becuase it is DW_64
+  override def FN_ADDUW    = "b00_000_0000_0000_1000__0001__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SLLIUW   = "b00_000_0000_1100_1000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
+  override def FN_SH1ADD   = "b00_000_0000_0000_0000__0010__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SH1ADDUW = "b00_000_0000_0000_1000__0010__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SH2ADD   = "b00_000_0000_0000_0000__0100__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SH2ADDUW = "b00_000_0000_0000_1000__0100__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SH3ADD   = "b00_000_0000_0000_0000__1000__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  override def FN_SH3ADDUW = "b00_000_0000_0000_1000__1000__00_0000_0000_0000_0001".U(SZ_ALU_FN.W)
+  // Zbb
+  override def FN_ROR      = "b00_000_0000_0010_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
+  override def FN_ROL      = "b00_000_0000_1110_0000__0001__00_0000_0000_0000_0010".U(SZ_ALU_FN.W)
+  override def FN_ANDN     = "b00_000_0000_0000_0010__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W)
+  override def FN_ORN      = "b00_000_0000_0000_0010__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W)
+  override def FN_XNOR     = "b00_000_0000_0000_0010__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W)
+  override def FN_REV8     = "b00_000_0000_0000_0000__0001__00_0001_0000_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_ORCB     = "b10_000_0000_0000_0000__0001__00_0010_0000_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_SEXTB    = "b00_000_0000_0000_0000__0001__00_0000_1000_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_SEXTH    = "b01_000_0000_0000_0000__0001__00_0000_0100_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_ZEXTH    = "b00_000_0000_0000_0000__0001__00_0000_0100_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_MAX      = "b00_000_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
+  override def FN_MAXU     = "b00_001_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
+  override def FN_MIN      = "b00_010_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
+  override def FN_MINU     = "b00_011_0000_0000_0011__0001__00_0000_0000_1000_0000".U(SZ_ALU_FN.W)
+  override def FN_CPOP     = "b00_000_0000_0000_0000__0001__00_0000_0001_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_CLZ      = "b00_000_1101_1110_0000__0001__00_0000_0010_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_CTZ      = "b00_000_1101_0000_0000__0001__00_0000_0010_0000_0000".U(SZ_ALU_FN.W)
+  // Zbs
+  override def FN_BCLR     = "b00_000_1110_1000_0100__0001__00_0000_0000_0000_0100".U(SZ_ALU_FN.W)
+  override def FN_BEXT     = "b00_000_1000_1000_0100__0001__00_0000_0000_0010_0000".U(SZ_ALU_FN.W)
+  override def FN_BINV     = "b00_000_1000_1000_0100__0001__00_0000_0000_0000_1000".U(SZ_ALU_FN.W)
+  override def FN_BSET     = "b00_000_1000_1000_0100__0001__00_0000_0000_0001_0000".U(SZ_ALU_FN.W)
+  // Zbk
+  override def FN_BREV8    = "b00_000_0000_0000_0000__0001__00_0010_0000_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_PACK     = "b00_000_0000_0000_0000__0001__00_0100_0000_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_PACKH    = "b00_000_0000_0000_0000__0001__00_1000_0000_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_ZIP      = "b00_000_0000_0000_0000__0001__01_0000_0000_0000_0000".U(SZ_ALU_FN.W)
+  override def FN_UNZIP    = "b00_000_0000_0000_0000__0001__10_0000_0000_0000_0000".U(SZ_ALU_FN.W)
+
+  override def FN_DIV  = FN_XOR
+  override def FN_DIVU = FN_SR
+  override def FN_REM  = FN_OR
+  override def FN_REMU = FN_AND
+
+  override def FN_MUL    = FN_ADD
+  override def FN_MULH   = FN_SL
+  override def FN_MULHSU = FN_SEQ
+  override def FN_MULHU  = FN_SNE
+}
+
+class ABLU(implicit p: Parameters) extends CoreModule()(p) with HasALUIO {
+  // note that it is reversed
+  val isSub :: isIn2Inv :: isZBS :: isUW :: Nil = io.fn(25,22).asBools
+  val isSRA :: isRotate :: isLeft :: isLeftZBS :: Nil = io.fn(29,26).asBools
+  val isCZ :: isBCLR :: isCZBCLR :: isCZZBS :: Nil = io.fn(33,30).asBools
+  val isUnsigned :: isInverted :: isSEQSNE :: Nil = io.fn(36,34).asBools
+  val isSEXT :: isORC :: Nil = io.fn(38,37).asBools
+  val shxadd1H = io.fn(21,18) // 4 bit
+  val out1H = io.fn(17,0)
+
+  // process input
+  // used by SUB, ANDN, ORN, XNOR
+  val in2_inv = Mux(isIn2Inv, ~io.in2, io.in2)
+  val shamt =
+    if (xLen == 32) io.in2(4,0)
+    else {
+      require(xLen == 64)
+      Cat(io.in2(5) & (io.dw === DW_64), io.in2(4,0))
+    }
+  val in1_ext =
+    if (xLen == 32) io.in1
+    else {
+      require(xLen == 64)
+      val in1_hi_orig = io.in1(63,32)
+      // note that CLZW uses rotate
+      val in1_hi_rotate = io.in1(31,0)
+      // note that sext fills 0 for ADDW/SUBW, but it works
+      val in1_hi_sext = Fill(32, isSRA & io.in1(31)) // 31 to 63 then to 64 in shout_r
+      val in1_hi_zext = Fill(32, 0.U)
+      val in1_hi = Mux(io.dw === DW_64,
+        Mux(isUW, in1_hi_zext, in1_hi_orig),
+        Mux(isRotate, in1_hi_rotate, in1_hi_sext))
+      Cat(in1_hi, io.in1(31,0))
+    }
+  // one arm: SL, ROL, SLLIUW, CLZ
+  // another arm: SR, SRA, ROR, CTZ, ADD, SUB, ZBS
+  // note that CLZW is not included here
+  // in1 capable of right hand operation
+  // isLeft
+  val in1_r = Mux(isLeft, Reverse(in1_ext), in1_ext)
+
+  // shifter
+  val shin = Mux(isZBS,
+    if (xLen == 32) (BigInt(1) << 31).U(32.W)
+    else {
+      require(xLen == 64)
+      (BigInt(1) << 63).U(64.W)
+    }, in1_r)
+  // TODO: Merge shift and rotate (manual barrel or upstream to Chisel)
+  val shout_r = (Cat(isSRA & shin(xLen-1), shin).asSInt >> shamt)(xLen-1,0)
+  val roout_r = shin.rotateRight(shamt)(xLen-1,0)
+  val shro_r = Mux(isRotate, roout_r, shout_r)
+  // one arm: SL, ROL, SLLIUW, ZBS
+  // another arm: SR, SRA, ROR
+  val shro = Mux(isLeftZBS, Reverse(shro_r), shro_r)
+
+  // adder
+  val adder_in1 =
+    Mux1H(shxadd1H, Seq(
+      if (xLen == 32) in1_r
+      else {
+        require(xLen == 64)
+        // for CLZW/CTZW
+        Mux(io.dw === DW_64, in1_r, Cat(Fill(32, 1.U(1.W)), in1_r(31,0)))
+      },
+      (in1_ext << 1)(xLen-1,0),
+      (in1_ext << 2)(xLen-1,0),
+      (in1_ext << 3)(xLen-1,0)))
+  // out = in1 - 1 when isCLZ/isCTZ
+  // note that when isCZ, isSub is 0 as ~0 = ~1+1 = -1
+  val adder_in2 = Mux(isCZ,
+    ~0.U(xLen.W), in2_inv)
+  // adder_out = adder_in1 + adder_in2 + isSub
+  val adder_out = (Cat(adder_in1, 1.U(1.W)) + Cat(adder_in2, isSub))(xLen,1)
+  io.adder_out := adder_out
+
+  // logic
+  // AND, OR, XOR
+  // ANDN, ORN, XNOR
+  // BCLR, BEXT, BINV, BSET
+  val out_inv = Mux(isCZBCLR, ~Mux(isBCLR, shro, adder_out), shro)
+  val logic_in2 = Mux(isCZZBS, out_inv, in2_inv)
+  // also BINV
+  val xor = adder_in1 ^ logic_in2
+  // also BCLR
+  val and = adder_in1 & logic_in2
+  // also BSET
+  val or = adder_in1 | logic_in2
+  val bext = and.orR
+
+  // SLT, SLTU
+  // BEQ, BNE, BLT, BGE
+  // MAX, MIN
+  val slt =
+    Mux(io.in1(xLen-1) === io.in2(xLen-1), adder_out(xLen-1),
+    Mux(isUnsigned, io.in2(xLen-1), io.in1(xLen-1)))
+  val cmp = isInverted ^ Mux(isSEQSNE, ~(xor.orR), slt)
+  io.cmp_out := cmp
+  // MAX, MAXU, MIN, MINU
+  val max_min = Mux(cmp, io.in2, io.in1)
+
+  // counter
+  // CLZ, CPOP, CTZ
+  val cpop = PopCount(
+    if (xLen == 32) io.in1
+    else {
+      require(xLen == 64)
+      Mux(io.dw === DW_64, io.in1, Cat(Fill(32, 0.U(1.W)), io.in1(31,0)))
+    })
+  // ctz_in = ~adder_out & adder_in1 // all zero or one hot
+  val ctz_in = and
+  val ctz_out = Cat(~ctz_in.orR, VecInit((0 to log2Ceil(xLen)-1).map(
+    x => {
+      val bits = ctz_in.asBools.zipWithIndex
+      VecInit(
+        bits
+          filter { case (_, i) => i % (1 << (x + 1)) >= (1 << x) }
+          map { case (b, _) => b }
+        ).asUInt.orR
+    }
+  ).toSeq).asUInt)
+
+  // ZEXT/SEXT
+  val exth = Cat(Fill(xLen-16, Mux(isSEXT, io.in1(15), 0.U)), io.in1(15,0))
+  val extb = Cat(Fill(xLen-8, io.in1(7)), io.in1(7,0))
+
+  // REV/ORC
+  def asBytes(in: UInt): Vec[UInt] = VecInit(in.asBools.grouped(8).map(VecInit(_).asUInt).toSeq)
+  val in1_bytes = asBytes(io.in1)
+  val rev8 = VecInit(in1_bytes.reverse.toSeq).asUInt
+  val orc_brev8 = VecInit(in1_bytes.map(x => {
+    val orc = Mux(x.orR, 0xFF.U(8.W), 0.U(8.W))
+    // BREV8 only in Zbk
+    if (usingBitManipCrypto)
+      Mux(isORC, orc, Reverse(x))
+    else orc
+  }).toSeq).asUInt
+
+  // pack
+  def sext(in: UInt): UInt = {
+    val in_hi_32 = Fill(32, in(31))
+    Cat(in_hi_32, in)
+  }
+  val pack = if (usingBitManipCrypto) {
+    if (xLen == 32) Cat(io.in2(xLen/2-1,0), io.in1(xLen/2-1,0))
+    else {
+      require(xLen == 64)
+      Mux(io.dw === DW_64,
+        Cat(io.in2(xLen/2-1,0), io.in1(xLen/2-1,0)),
+        sext(Cat(io.in2(xLen/4-1,0), io.in1(xLen/4-1,0))))
+    }
+  } else 0.U
+  val packh = if (usingBitManipCrypto) Cat(0.U((xLen-16).W), io.in2(7,0), io.in1(7,0)) else 0.U
+
+  // zip
+  val zip = if (xLen == 32 && usingBitManipCrypto) {
+    val lo = io.in1(15,0).asBools
+    val hi = io.in1(31,16).asBools
+    VecInit(lo.zip(hi).map { case (l, h) => VecInit(Seq(l, h)).asUInt }).asUInt
+  } else 0.U
+  val unzip = if (xLen == 32 && usingBitManipCrypto) {
+    val bits = io.in1.asBools.zipWithIndex
+    val lo = VecInit(bits filter { case (_, i) => i % 2 == 0 } map { case (b, _) => b }).asUInt
+    val hi = VecInit(bits filter { case (_, i) => i % 2 != 0 } map { case (b, _) => b }).asUInt
+    Cat(hi, lo)
+  } else 0.U
+
+  val out = Mux1H(out1H, Seq(
+    adder_out,
+    shro,
+    and,
+    xor,
+    //
+    or,
+    bext,
+    cmp,
+    max_min,
+    //
+    cpop,
+    ctz_out,
+    exth,
+    extb,
+    //
+    rev8,
+    orc_brev8,
+    pack,
+    packh,
+    //
+    zip,
+    unzip))
+
+  val out_w =
+    if (xLen == 32) out
+    else {
+      require(xLen == 64)
+      Mux(io.dw === DW_64, out, Cat(Fill(32, out(31)), out(31,0)))
+    }
+  io.out := out_w
+}