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Zk(Zbk, Zkn, Zks)/Zb: Scalar Cryptography/Bitmanip Extension #2950

Merged
merged 104 commits into from
Jan 18, 2023
Merged

Zk(Zbk, Zkn, Zks)/Zb: Scalar Cryptography/Bitmanip Extension #2950

merged 104 commits into from
Jan 18, 2023

Commits on Mar 15, 2022

  1. add the Zbk extension for Bitmanip instructions supporting cryptography 

    fix decode due to the add of H extension commit

Related to 185cac8
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  2. Zbk: implement rotate

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  3. Zbk: implement logic

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  4. Zbk: implement pack

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  5. Zbk: implement rev

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  6. Zbk: implement zip

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  7. Zbk: implement xperm

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  8. Zbk: xperm cheaper impl

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  9. Zbk: add zbkc decode

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  10. Zbk: implement clmul

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  11. Zbk: implement out mux

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  12. Zbk: clmul: fix off by one

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  13. zbk: fix compile

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Commits on Mar 16, 2022

  1. Zbk: update instruction decode for Zbk

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  2. bk: fix config 

    Cherry-pick part of (54a6cdd)
Zbk: add the Zbk implementation for RV64
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  3. Zbk: a small correction

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  4. decode: add the support for the Zkn extension 

    Merge conflicts with (185cac8)
Add hypervisor extension (chipsalliance#2841)
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  5. Use asBytes/asNibbles helper

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  6. zkn: implement aes enc/dec

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  7. zkn: implement aes ks

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  8. zkn: aes ks1 reuse sbox in enc

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  9. zkn: implement sha

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  10. ZK: add the support for the Zks extension.

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  11. zks: implement sm3/4

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  12. zkn, zks: implement out mux

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Commits on Mar 18, 2022

  1. zk: fix compile

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Commits on Mar 19, 2022

  1. zbk: fix packw/xperm

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  2. zkn: fix aes64ks1m due to not merged datapath

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  3. zks: sm4: fix UInt length after left shift

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  4. zkn, zks: aes32, sm4 fix leftRotate to rightRotate

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  5. zkn: xperm: fix input

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  6. zkn: fix sha512 for rv32

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Commits on Apr 1, 2022

  1. Zb: move andn/orn/xnor into ALU

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  2. Zb: move rotate into ALU

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  3. ALU: stop using when

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  4. Zb: add max/min

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  5. Zb: add clz/cpop/ctz

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  6. Zb: add sext/bext

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  7. Zb: add rev8/orc

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Commits on Apr 2, 2022

  1. Zb: add Zba

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  2. Zb: add Zbs

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  3. Zb: add clmulr

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Commits on Apr 3, 2022

  1. Zbb: clz/ctz now do not need PopCount

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Commits on Apr 4, 2022

  1. ALU: refactor

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Commits on Apr 9, 2022

  1. Rename refactored ALU into ABLU

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Commits on Apr 16, 2022

  1. ABLU: ctz: Fix when all 0 

    When all 0, it is 32/64, which can not be represented
by log(32)/log(64)
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  2. ABLU: implment ALU side pla

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  3. ABLU: fix compile

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Commits on Apr 17, 2022

  1. Instructions: sync from riscv-opcodes 

    The current Instructions.scala is not up-to-date with riscv-opcodes

Previous changes on this file seems to be adding new instructions manually,
this can be inferred from
riscv/riscv-opcodes@e2ebbf5
which changed the name from parse-opcodes to parse_opcodes
thus this PR reorders a lot of instructions and CSRs
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  2. CSR: rename dscratch to dscratch0

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  3. Instructions: Separate rocket custom instructions 

    As standard instructions are synced from riscv-opcodes
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  4. Instructions: Separate NMI insts and CSRs 

    Rocket already implemented NMI in chipsalliance#2711,
however, riscv-opcodes currently does not have NMI
as it is a WIP (See riscv/riscv-opcodes#67)

To avoid generating Instructions.scala from a patched riscv-opcodes,
putting NMI related insts/CSRs into CustomInstructions is reasonable.
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  5. Instructions: use chisel3

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  6. ABLU: fill the decode table for Zb

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Commits on Apr 18, 2022

  1. IDecode: add Zb/Zk

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  2. IDecode: fix for rv32

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  3. add zba64 decode

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  4. ABLU: fix ctrl sig for maxu/min

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  5. ABLU: fix ctwz/clzw zba64 and zbs

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Commits on Apr 23, 2022

  1. zk: sbox use ny93 instead of ROM 

    Better area
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  2. IDecode: cleanup zkn/zks

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  3. Add Zb/Zk related configs; cleanup code according to config

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Commits on Apr 25, 2022

  1. Merge remote-tracking branch 'origin/master' into Zk-chisel

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Commits on May 6, 2022

  1. Add aes64ks1i exception

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  2. Merge branch 'master' into Zk-chisel

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  3. IDecode: Fix Zb due to Instructions32 change

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  4. Fix error from scalafix

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Commits on May 9, 2022

  1. Move pla into decode

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Commits on May 15, 2022

  1. fix ALU.FN when using ABLU

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Commits on May 16, 2022

  1. Merge pull request #2 from cyyself/Zk-chisel 

    fix ALU.FN when using ABLU
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  2. Fix license

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  3. Move BarrelShifter into util

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  4. Rename ALUClass to AbstractAlu

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Commits on May 17, 2022

  1. Move usingABLU to HasRocketCoreParams

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Commits on Jun 13, 2022

  1. Merge remote-tracking branch 'origin/master' into Zk-chisel

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Commits on Jun 15, 2022

  1. IDecode: use DW_XPR for branch insts 

    The DW signal for branch insts was X,
and making it Bool(true) is fixing it
to one of the possible values.

No matter it is DW_X or DW_XPR, ALU would
function happily for RV32/RV64.

However, for RV64 ABLU, branch inst
depends on cmp, then xor, then adder_in1,
and if io.dw == 0, namely DW_32
and possibly DW_X (depending on decoder)
the higher 32 bits of adder_in1 is filled
with 1, then ABLU would malfunction.
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  2. CryptoNIST: refactor ctrl signals

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  3. CryptoSM: refactor ctrl signals

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  4. Move pla into decode

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  5. BitManipCrypto: use Mux1H for output

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  6. BitManipCrypto: only instantiate clmul when not usingBitManipCrypto

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  7. RocketCore: use Mux1H for mem_reg_wdata to reduce latency

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  8. ABLU: cleanup

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Commits on Jan 5, 2023

  1. Merge branch 'master' into Zk-chisel

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Commits on Jan 7, 2023

  1. Merge branch 'master' into Zk-chisel-new

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  2. Fix for chisel3 style and new PRs

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  3. Fix decoding for zbs imm

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Commits on Jan 10, 2023

  1. Merge branch 'master' into Zk-chisel-new

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  2. Add CI for Zb/Zk arch-test

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Commits on Jan 14, 2023

  1. Remove useABLU

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  2. Fix Bitmanip name

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 14, 2023
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  3. Add Bitmanip/Crypto related isa string in DTS

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 14, 2023
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  4. Instantiate BitManipCrypto earlier 

    Make both isaDTS and usingBitManipCrypto happy
    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 14, 2023
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  5. Merge branch 'master' into Zk-chisel

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 14, 2023
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Commits on Jan 15, 2023

  1. Add comment on B misa bit

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 15, 2023
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  2. Refactor ALUFN

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 15, 2023
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  3. Refactor other ctrl signals

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 15, 2023
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  4. Pass alufn to Multipler

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 15, 2023
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Commits on Jan 16, 2023

  1. More default ALUFN

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 16, 2023
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Commits on Jan 17, 2023

  1. Refactors to ease migration burden

    @jerryz123
    jerryz123 committed Jan 17, 2023
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  2. Merge pull request #4 from chipsalliance/Zk-chisel-fixes 

    Refactors to ease migration burden
    @ZenithalHourlyRate
    ZenithalHourlyRate authored Jan 17, 2023
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  3. Fix format

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 17, 2023
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  4. Fix int ctrl sigs fn width

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 17, 2023
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Commits on Jan 18, 2023

  1. Add isa string in bulk

    @ZenithalHourlyRate
    ZenithalHourlyRate committed Jan 18, 2023
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