L1TLB: fix support for configurable Sets/Ways

src/main/scala/diplomaticobjectmodel/logicaltree/RocketLogicalTreeNode.scala

@@ -30,6 +30,7 @@ class DCacheLogicalTreeNode(dcache: HellaCache, deviceOpt: Option[SimpleDevice],
         dataMemorySizeBytes = params.nSets * params.nWays * params.blockBytes,
         dataECC = params.dataECC.map(OMECC.fromString),
         tagECC = params.tagECC.map(OMECC.fromString),
+        nTLBEntries = params.nTLBSets * params.nTLBWays,
         nTLBSets = params.nTLBSets,
         nTLBWays = params.nTLBWays,
         memories = dcache.getOMSRAMs(),
@@ -50,6 +51,7 @@ class ICacheLogicalTreeNode(icache: ICache, deviceOpt: Option[SimpleDevice], par
         dataMemorySizeBytes = params.nSets * params.nWays * params.blockBytes,
         dataECC = params.dataECC.map(OMECC.fromString),
         tagECC = params.tagECC.map(OMECC.fromString),
+        nTLBEntries = params.nTLBSets * params.nTLBWays,
         nTLBSets = params.nTLBSets,
         nTLBWays = params.nTLBWays,
         maxTimSize = params.nSets * (params.nWays-1) * params.blockBytes,

src/main/scala/diplomaticobjectmodel/model/OMCaches.scala

@@ -25,6 +25,7 @@ case class OMICache(
   dataMemorySizeBytes: Int,
   dataECC: Option[OMECC],
   tagECC: Option[OMECC],
+  nTLBEntries: Int,
   nTLBSets: Int,
   nTLBWays: Int,
   maxTimSize: Int,
@@ -41,6 +42,7 @@ case class OMDCache(
   dataMemorySizeBytes: Int,
   dataECC: Option[OMECC],
   tagECC: Option[OMECC],
+  nTLBEntries: Int,
   nTLBSets: Int,
   nTLBWays: Int,
   memories: Seq[OMSRAM],

src/main/scala/rocket/TLB.scala

@@ -146,7 +146,7 @@ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boo
 
 case class TLBConfig(
     nSets: Int,
-    nEntries: Int,
+    nWays: Int,
     nSectors: Int = 4,
     nSuperpageEntries: Int = 4)
 
@@ -162,7 +162,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
   val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
   val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits)
   val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2)
-  val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nEntries / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false))))
+  val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false))))
   val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true)))
   val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false)))
   def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries
@@ -324,7 +324,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
   val tlb_hit = real_hits.orR
   val tlb_miss = vm_enabled && !bad_va && !tlb_hit
 
-  val sectored_plru = new SetAssocLRU(cfg.nSets, cfg.nEntries, "plru")
+  val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries(0).size, "plru")
   val superpage_plru = new PseudoLRU(superpage_entries.size)
   when (io.req.valid && vm_enabled) {
     when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) }

src/main/scala/tile/L1Cache.scala

@@ -13,7 +13,7 @@ trait L1CacheParams {
   def nWays:         Int
   def rowBits:       Int
   def nTLBSets:      Int
-  def nTLBWays:   Int
+  def nTLBWays:      Int
   def blockBytes:    Int // TODO this is ignored in favor of p(CacheBlockBytes) in BaseTile
 }
 

src/main/scala/util/Replacement.scala

@@ -56,6 +56,7 @@ abstract class SeqReplacementPolicy {
 
 abstract class SetAssocReplacementPolicy {
   def access(set: UInt, touch_way: UInt): Unit
+  def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit
   def way(set: UInt): UInt
 }
 
@@ -301,6 +302,17 @@ class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocRepl
     state_vec(set) := logic.get_next_state(state_vec(set), touch_way)
   }
 
+  def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = {
+    require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways")
+    for (set <- 0 until n_sets) {
+      val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) =>
+        Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)}
+      when (set_touch_ways.map(_.valid).orR) {
+        state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways)
+      }
+    }
+  }
+
   def way(set: UInt) = logic.get_replace_way(state_vec(set))
 
 }