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Changed the function called cover to mincover. Tightened the bound for the fragmenter by adding shrinktransfer. Added comment. #2571

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merged 8 commits into from
Jul 27, 2020
Merged

Changed the function called cover to mincover. Tightened the bound for the fragmenter by adding shrinktransfer. Added comment. #2571

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d7758df
added comment
brrmorre Jul 20, 2020
73a5894
replaced with mincover
brrmorre Jul 20, 2020
d4c418b
shrinktransfer
brrmorre Jul 20, 2020
ea469ef
update
brrmorre Jul 20, 2020
323585e
changed name of cover
brrmorre Jul 22, 2020
d80cf77
bug fix
brrmorre Jul 22, 2020
c022dcf
Update Parameters.scala
brrmorre Jul 24, 2020
e8f79b1
mincover
brrmorre Jul 24, 2020
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1 change: 1 addition & 0 deletions src/main/scala/amba/ahb/ToTL.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHB
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.map { m =>
// This value should be constrained by a data width parameter that flows from masters to slaves
// AHB fixed length transfer size maximum is 16384 = 1024 * 16 bits, hsize is capped at 111 = 1024 bit transfer size and hburst is capped at 111 = 16 beat burst
TLMasterParameters.v2(
name = m.name,
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/amba/axis/Parameters.scala
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Expand Up @@ -61,7 +61,7 @@ class AXISSlavePortParameters private (
beatBytes.foreach { b => require(isPow2(b)) }

val endDestinationId = slaves.map(_.destinationId).max + 1
val supportsCover = TransferSizes.cover(slaves.map(_.supportsSizes))
val supportsCover = TransferSizes.mincover(slaves.map(_.supportsSizes))
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def v1copy(
slaves: Seq[AXISSlaveParameters] = slaves,
Expand Down Expand Up @@ -146,7 +146,7 @@ class AXISMasterPortParameters private (
beatBytes.foreach { b => require(isPow2(b)) }

val endSourceId = masters.map(_.sourceId.end).max
val emitsCover = TransferSizes.cover(masters.map(_.emitsSizes))
val emitsCover = TransferSizes.mincover(masters.map(_.emitsSizes))
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def v1copy(
masters: Seq[AXISMasterParameters] = masters,
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/diplomacy/Parameters.scala
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Expand Up @@ -100,7 +100,7 @@ case class TransferSizes(min: Int, max: Int)

// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def cover(x: TransferSizes) = {
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
Expand All @@ -117,7 +117,7 @@ object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)

def cover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ cover _)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)

implicit def asBool(x: TransferSizes) = !x.none
Expand Down
16 changes: 8 additions & 8 deletions src/main/scala/tilelink/Fragmenter.scala
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Expand Up @@ -60,14 +60,14 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = c.masters.map(_.emits.acquireT) .reduce(_ cover _),
acquireB = c.masters.map(_.emits.acquireB) .reduce(_ cover _),
arithmetic = c.masters.map(_.emits.arithmetic).reduce(_ cover _),
logical = c.masters.map(_.emits.logical) .reduce(_ cover _),
get = c.masters.map(_.emits.get) .reduce(_ cover _),
putFull = c.masters.map(_.emits.putFull) .reduce(_ cover _),
putPartial = c.masters.map(_.emits.putPartial).reduce(_ cover _),
hint = c.masters.map(_.emits.hint) .reduce(_ cover _)
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
)},
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44 changes: 22 additions & 22 deletions src/main/scala/tilelink/Parameters.scala
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Expand Up @@ -31,15 +31,15 @@ case class TLMasterToSlaveTransferSizes(
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def cover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .cover(rhs.acquireT),
acquireB = acquireB .cover(rhs.acquireB),
arithmetic = arithmetic.cover(rhs.arithmetic),
logical = logical .cover(rhs.logical),
get = get .cover(rhs.get),
putFull = putFull .cover(rhs.putFull),
putPartial = putPartial.cover(rhs.putPartial),
hint = hint .cover(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
Expand Down Expand Up @@ -101,14 +101,14 @@ case class TLSlaveToMasterTransferSizes(
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def cover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .cover(rhs.probe),
arithmetic = arithmetic.cover(rhs.arithmetic),
logical = logical .cover(rhs.logical),
get = get .cover(rhs.get),
putFull = putFull .cover(rhs.putFull),
putPartial = putPartial.cover(rhs.putPartial),
hint = hint .cover(rhs.hint)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
Expand Down Expand Up @@ -306,7 +306,7 @@ class TLSlaveParameters private(
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
setName: Option[String] = setName,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
Expand All @@ -320,7 +320,7 @@ class TLSlaveParameters private(
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = setName,
setName = name,
address = address,
regionType = regionType,
executable = executable,
Expand Down Expand Up @@ -420,7 +420,7 @@ object TLSlaveParameters {
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
setName: Option[String] = None,
name: Option[String] = None,
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regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
Expand All @@ -433,7 +433,7 @@ object TLSlaveParameters {
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = setName,
setName = name,
address = address,
regionType = regionType,
executable = executable,
Expand Down Expand Up @@ -570,7 +570,7 @@ class TLSlavePortParameters private(
val allSupportHint = allSupports.hint

// Operation supported by at least one outward Slaves
val anySupports = slaves.map(_.supports).reduce(_ cover _)
val anySupports = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupports.acquireT.none
val anySupportAcquireB = !anySupports.acquireB.none
val anySupportArithmetic = !anySupports.arithmetic.none
Expand Down