TileLink Diplomacy parameters supportsProbe -> supports.probe

src/main/scala/tilelink/BankBinder.scala

@@ -24,13 +24,13 @@ case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCus
   def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] =
     (p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy(
       visibility         = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))},
-      supportsProbe      = c.supportsProbe      intersect maxXfer,
-      supportsArithmetic = c.supportsArithmetic intersect maxXfer,
-      supportsLogical    = c.supportsLogical    intersect maxXfer,
-      supportsGet        = c.supportsGet        intersect maxXfer,
-      supportsPutFull    = c.supportsPutFull    intersect maxXfer,
-      supportsPutPartial = c.supportsPutPartial intersect maxXfer,
-      supportsHint       = c.supportsHint       intersect maxXfer)})}
+      supportsProbe      = c.supports.probe      intersect maxXfer,
+      supportsArithmetic = c.supports.arithmetic intersect maxXfer,
+      supportsLogical    = c.supports.logical    intersect maxXfer,
+      supportsGet        = c.supports.get        intersect maxXfer,
+      supportsPutFull    = c.supports.putFull    intersect maxXfer,
+      supportsPutPartial = c.supports.putPartial intersect maxXfer,
+      supportsHint       = c.supports.hint       intersect maxXfer)})}
 
   def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] =
     (p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m =>

src/main/scala/tilelink/Broadcast.scala

@@ -90,7 +90,7 @@ class TLBroadcast(params: TLBroadcastParams)(implicit p: Parameters) extends Laz
 
       require (params.lineBytes >= edgeOut.manager.beatBytes)
       // For the probe walker, we need to identify all the caches
-      val caches = clients.filter(_.supportsProbe).map(_.sourceId)
+      val caches = clients.filter(_.supports.probe).map(_.sourceId)
       val cache_targets = caches.map(c => c.start.U)
 
       // Create the probe filter

src/main/scala/tilelink/CacheCork.scala

@@ -32,7 +32,7 @@ class TLCacheCork(unsafe: Boolean = false, sinkIds: Int = 8)(implicit p: Paramet
         out <> in
       } else {
         val clients = edgeIn.client.clients
-        val caches = clients.filter(_.supportsProbe)
+        val caches = clients.filter(_.supports.probe)
         require (clients.size == 1 || caches.size == 0 || unsafe, s"Only one client can safely use a TLCacheCork; ${clients.map(_.name)}")
         require (caches.size <= 1 || unsafe, s"Only one caching client allowed; ${clients.map(_.name)}")
         edgeOut.manager.managers.foreach { case m =>

src/main/scala/tilelink/Filter.scala

@@ -17,13 +17,13 @@ class TLFilter(
       val out = cfilter(c)
       out.map { o => // Confirm the filter only REMOVES capability
         require (c.sourceId.contains(o.sourceId))
-        require (c.supportsProbe.contains(o.supportsProbe))
-        require (c.supportsArithmetic.contains(o.supportsArithmetic))
-        require (c.supportsLogical.contains(o.supportsLogical))
-        require (c.supportsGet.contains(o.supportsGet))
-        require (c.supportsPutFull.contains(o.supportsPutFull))
-        require (c.supportsPutPartial.contains(o.supportsPutPartial))
-        require (c.supportsHint.contains(o.supportsHint))
+        require (c.supports.probe.contains(o.supports.probe))
+        require (c.supports.arithmetic.contains(o.supports.arithmetic))
+        require (c.supports.logical.contains(o.supports.logical))
+        require (c.supports.get.contains(o.supports.get))
+        require (c.supports.putFull.contains(o.supports.putFull))
+        require (c.supports.putPartial.contains(o.supports.putPartial))
+        require (c.supports.hint.contains(o.supports.hint))
         require (!c.requestFifo || o.requestFifo)
       }
       out
@@ -146,11 +146,11 @@ object TLFilter
   }
   // hide all caching clients
   def cHideCaching: ClientFilter = { c =>
-    if (c.supportsProbe) None else Some(c)
+    if (c.supports.probe) None else Some(c)
   }
   // onyl caching clients are visible
   def cSelectCaching: ClientFilter = { c =>
-    if (c.supportsProbe) Some(c) else None
+    if (c.supports.probe) Some(c) else None
   }
 
   // default application applies neither type of filter unless overridden

src/main/scala/tilelink/Parameters.scala

@@ -859,24 +859,24 @@ class TLMasterParameters private(
 
   require (!sourceId.isEmpty)
   require (!visibility.isEmpty)
-  require (supportsPutFull.contains(supportsPutPartial))
+  require (supports.putFull.contains(supports.putPartial))
   // We only support these operations if we support Probe (ie: we're a cache)
-  require (supportsProbe.contains(supportsArithmetic))
-  require (supportsProbe.contains(supportsLogical))
-  require (supportsProbe.contains(supportsGet))
-  require (supportsProbe.contains(supportsPutFull))
-  require (supportsProbe.contains(supportsPutPartial))
-  require (supportsProbe.contains(supportsHint))
+  require (supports.probe.contains(supports.arithmetic))
+  require (supports.probe.contains(supports.logical))
+  require (supports.probe.contains(supports.get))
+  require (supports.probe.contains(supports.putFull))
+  require (supports.probe.contains(supports.putPartial))
+  require (supports.probe.contains(supports.hint))
 
   visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
 
   val maxTransfer = List(
-    supportsProbe.max,
-    supportsArithmetic.max,
-    supportsLogical.max,
-    supportsGet.max,
-    supportsPutFull.max,
-    supportsPutPartial.max).max
+    supports.probe.max,
+    supports.arithmetic.max,
+    supports.logical.max,
+    supports.get.max,
+    supports.putFull.max,
+    supports.putPartial.max).max
 
   def infoString = {
     s"""Master Name = ${name}
@@ -1120,22 +1120,22 @@ class TLMasterPortParameters private(
   }
 
   // Operation sizes supported by all inward Masters
-  val allSupportProbe      = masters.map(_.supportsProbe)     .reduce(_ intersect _)
-  val allSupportArithmetic = masters.map(_.supportsArithmetic).reduce(_ intersect _)
-  val allSupportLogical    = masters.map(_.supportsLogical)   .reduce(_ intersect _)
-  val allSupportGet        = masters.map(_.supportsGet)       .reduce(_ intersect _)
-  val allSupportPutFull    = masters.map(_.supportsPutFull)   .reduce(_ intersect _)
-  val allSupportPutPartial = masters.map(_.supportsPutPartial).reduce(_ intersect _)
-  val allSupportHint       = masters.map(_.supportsHint)      .reduce(_ intersect _)
+  val allSupportProbe      = masters.map(_.supports.probe)     .reduce(_ intersect _)
+  val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
+  val allSupportLogical    = masters.map(_.supports.logical)   .reduce(_ intersect _)
+  val allSupportGet        = masters.map(_.supports.get)       .reduce(_ intersect _)
+  val allSupportPutFull    = masters.map(_.supports.putFull)   .reduce(_ intersect _)
+  val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
+  val allSupportHint       = masters.map(_.supports.hint)      .reduce(_ intersect _)
 
   // Operation is supported by at least one master
-  val anySupportProbe      = masters.map(!_.supportsProbe.none)     .reduce(_ || _)
-  val anySupportArithmetic = masters.map(!_.supportsArithmetic.none).reduce(_ || _)
-  val anySupportLogical    = masters.map(!_.supportsLogical.none)   .reduce(_ || _)
-  val anySupportGet        = masters.map(!_.supportsGet.none)       .reduce(_ || _)
-  val anySupportPutFull    = masters.map(!_.supportsPutFull.none)   .reduce(_ || _)
-  val anySupportPutPartial = masters.map(!_.supportsPutPartial.none).reduce(_ || _)
-  val anySupportHint       = masters.map(!_.supportsHint.none)      .reduce(_ || _)
+  val anySupportProbe      = masters.map(!_.supports.probe.none)     .reduce(_ || _)
+  val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
+  val anySupportLogical    = masters.map(!_.supports.logical.none)   .reduce(_ || _)
+  val anySupportGet        = masters.map(!_.supports.get.none)       .reduce(_ || _)
+  val anySupportPutFull    = masters.map(!_.supports.putFull.none)   .reduce(_ || _)
+  val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
+  val anySupportHint       = masters.map(!_.supports.hint.none)      .reduce(_ || _)
 
   // These return Option[TLMasterParameters] for your convenience
   def find(id: Int) = masters.find(_.sourceId.contains(id))
@@ -1505,7 +1505,7 @@ class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry
   private val sorted = tl.masters.sortBy(_.sourceId)
 
   val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
-    TLSourceIdMapEntry(c.sourceId, c.name, c.supportsProbe, c.requestFifo)
+    TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
   }
 }
 

src/main/scala/tilelink/ToAXI4.scala

@@ -33,7 +33,7 @@ class TLtoAXI4IdMap(tl: TLMasterPortParameters, axi4: AXI4MasterPortParameters)
   private val sorted = tl.clients.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType)
 
   val mapping: Seq[TLToAXI4IdMapEntry] = (sorted zip axi4.masters) map { case (c, m) =>
-    TLToAXI4IdMapEntry(m.id, c.sourceId, c.name, c.supportsProbe, c.requestFifo)
+    TLToAXI4IdMapEntry(m.id, c.sourceId, c.name, c.supports.probe, c.requestFifo)
   }
 }
 
@@ -278,10 +278,10 @@ object TLToAXI4
   }
 
   def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = {
-    if ( a.supportsProbe && !b.supportsProbe) return false
-    if (!a.supportsProbe &&  b.supportsProbe) return true
-    if ( a.requestFifo   && !b.requestFifo  ) return false
-    if (!a.requestFifo   &&  b.requestFifo  ) return true
+    if ( a.supports.probe && !b.supports.probe) return false
+    if (!a.supports.probe &&  b.supports.probe) return true
+    if ( a.requestFifo    && !b.requestFifo   ) return false
+    if (!a.requestFifo    &&  b.requestFifo   ) return true
     return false
   }
 }