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TLB: Check for PutPartial support separately from PutFull #2503

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merged 4 commits into from
Jun 8, 2020
Merged

TLB: Check for PutPartial support separately from PutFull #2503

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2836549
TLB: Check for PutPartial support separately from PutFull
aswaterman Jun 5, 2020
f34d7ca
Remove newly unnecessary D$ PutPartial assertion
aswaterman Jun 5, 2020
35e7da9
D$: break up AMOALUs if coreDataBits > xLen
aswaterman Jun 5, 2020
f2a71ae
Temporarily disable tests hitting OOM in Actions
aswaterman Jun 5, 2020
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1 change: 0 additions & 1 deletion src/main/scala/rocket/DCache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -897,7 +897,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// We could consider turning some of these into dynamic PMA checks.
require(!m.supportsAcquireB || m.supportsGet, "With a vector unit, cacheable memory must support Get")
require(!m.supportsAcquireT || m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial")
require(!m.supportsPutFull || m.supportsPutPartial, "With a vector unit, writable memory must support PutPartial")
}
}

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8 changes: 8 additions & 0 deletions src/main/scala/rocket/TLB.scala
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Expand Up @@ -64,6 +64,7 @@ class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) {
val pw = Bool()
val px = Bool()
val pr = Bool()
val ppp = Bool() // PutPartial
val pal = Bool() // AMO logical
val paa = Bool() // AMO arithmetic
val eff = Bool() // get/put effects
Expand Down Expand Up @@ -199,6 +200,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
val deny_access_to_debug = mpu_priv <= PRV.M && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false)
val prot_r = fastCheck(_.supportsGet) && !deny_access_to_debug && pmp.io.r
val prot_w = fastCheck(_.supportsPutFull) && !deny_access_to_debug && pmp.io.w
val prot_pp = fastCheck(_.supportsPutPartial)
val prot_al = fastCheck(_.supportsLogical)
val prot_aa = fastCheck(_.supportsArithmetic)
val prot_x = fastCheck(_.executable) && !deny_access_to_debug && pmp.io.x
Expand Down Expand Up @@ -226,6 +228,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
newEntry.pr := prot_r
newEntry.pw := prot_w
newEntry.px := prot_x
newEntry.ppp := prot_pp
newEntry.pal := prot_al
newEntry.paa := prot_aa
newEntry.eff := prot_eff
Expand Down Expand Up @@ -260,8 +263,10 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~ptw_ae_array
val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt)
val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt)
val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt)
val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt)
val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt)
val ppp_array_if_cached = ppp_array | c_array
val paa_array_if_cached = paa_array | Mux(usingAtomicsInCache, c_array, 0.U)
val pal_array_if_cached = pal_array | Mux(usingAtomicsInCache, c_array, 0.U)
val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt)
Expand All @@ -280,6 +285,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
val cmd_lrsc = Bool(usingAtomics) && io.req.bits.cmd.isOneOf(M_XLR, M_XSC)
val cmd_amo_logical = Bool(usingAtomics) && isAMOLogical(io.req.bits.cmd)
val cmd_amo_arithmetic = Bool(usingAtomics) && isAMOArithmetic(io.req.bits.cmd)
val cmd_put_partial = io.req.bits.cmd === M_PWR
val cmd_read = isRead(io.req.bits.cmd)
val cmd_write = isWrite(io.req.bits.cmd)
val cmd_write_perms = cmd_write ||
Expand All @@ -292,9 +298,11 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
val ae_ld_array = Mux(cmd_read, ae_array | ~pr_array, 0.U)
val ae_st_array =
Mux(cmd_write_perms, ae_array | ~pw_array, 0.U) |
Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) |
Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) |
Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U)
val must_alloc_array =
Mux(cmd_put_partial, ~ppp_array, 0.U) |
Mux(cmd_amo_logical, ~paa_array, 0.U) |
Mux(cmd_amo_arithmetic, ~pal_array, 0.U) |
Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U)
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