TLB: Check for PutPartial support separately from PutFull #2503
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Previously, the TLB would report that M_PWR (PutPartial) was permissible anywhere that M_XWR (PutFull) was. This is fine for cache transactions, since the caches can handle PutPartial internally. It's not fine for uncached transactions, since PutFull support does not imply PutPartial support. So, check for PutPartial support separately, similar to AMOs. If the access is cached, assume the access can proceed, since it'll be handled in cache. If the access is uncached, check the PMA. Rocket never issues M_PWR, so there's no functional change on that front.
ingallsj
approved these changes
Jun 5, 2020
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Similar to #2502 -- "Killed", so probably OOM, not a definitive test failure. |
Rather than having one big ALU with a coreDataBits-sized adder, have two smaller ALUs with shorter critical paths. This is just a QoR improvement for e.g. RV32D, which has xLen=32 and coreDataBits=64. For other uses of the D$ that require coreDataBits>64, it's also a functional fix.
ingallsj
approved these changes
Jun 5, 2020
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Previously, the TLB would report that M_PWR (PutPartial) was permissible
anywhere that M_XWR (PutFull) was. This is fine for cache transactions,
since the caches can handle PutPartial internally. It's not fine for
uncached transactions, since PutFull support does not imply PutPartial
support.
So, check for PutPartial support separately, similar to AMOs. If the
access is cached, assume the access can proceed, since it'll be handled
in cache. If the access is uncached, check the PMA.
Rocket never issues M_PWR, so there's no functional change on that front.
Type of change: other enhancement
Impact: API addition (no impact on existing code)