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subsystem: add an optional node to use for assigning hartids #2447

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merged 2 commits into from
May 5, 2020
Merged

subsystem: add an optional node to use for assigning hartids #2447

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6a31846
subsystem: add an optional node to use for assigning hartids
terpstra May 2, 2020
670c458
RocketSuiteC: remove travis_wait from relatively short job
terpstra May 5, 2020
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2 changes: 1 addition & 1 deletion .travis.yml
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Expand Up @@ -104,7 +104,7 @@ jobs:
- <<: *test
script:
- travis_wait 80 make emulator-ndebug -C regression SUITE=RocketSuiteC JVM_MEMORY=3G
- travis_wait 80 make emulator-regression-tests -C regression SUITE=RocketSuiteC JVM_MEMORY=3G
- make emulator-regression-tests -C regression SUITE=RocketSuiteC JVM_MEMORY=3G
- <<: *test
script:
- travis_wait 80 make emulator-ndebug -C regression SUITE=Miscellaneous JVM_MEMORY=3G
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5 changes: 5 additions & 0 deletions src/main/scala/diplomacy/package.scala
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Expand Up @@ -3,6 +3,7 @@
package freechips.rocketchip

import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
import chisel3.Data
import freechips.rocketchip.config.Parameters
import scala.language.implicitConversions

Expand Down Expand Up @@ -64,4 +65,8 @@ package object diplomacy
implicit def moduleValue[T](value: ModuleValue[T]): T = value.getWrappedValue

implicit def noCrossing(value: NoCrossing.type): ClockCrossingType = SynchronousCrossing(BufferParams.none)

type BundleBridgeInwardNode[T <: Data] = InwardNodeHandle[BundleBridgeParams[T], BundleBridgeNull, BundleBridgeParams[T], T]
type BundleBridgeOutwardNode[T <: Data] = OutwardNodeHandle[BundleBridgeParams[T], BundleBridgeNull, BundleBridgeParams[T], T]
type BundleBridgeNode[T <: Data] = NodeHandle[BundleBridgeParams[T], BundleBridgeNull, BundleBridgeParams[T], T, BundleBridgeParams[T], BundleBridgeNull, BundleBridgeParams[T], T]
}
21 changes: 19 additions & 2 deletions src/main/scala/subsystem/RocketSubsystem.scala
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Expand Up @@ -12,6 +12,8 @@ import freechips.rocketchip.diplomaticobjectmodel.logicaltree._
import freechips.rocketchip.diplomaticobjectmodel.model._
import freechips.rocketchip.tile._

case object HartPrefixKey extends Field[Boolean](false)

// TODO: how specific are these to RocketTiles?
case class TileMasterPortParams(
buffers: Int = 0,
Expand Down Expand Up @@ -80,14 +82,29 @@ class RocketSubsystem(implicit p: Parameters) extends BaseSubsystem
// add Mask ROM devices
val maskROMs = p(PeripheryMaskROMKey).map { MaskROM.attach(_, cbus) }

val hartPrefixNode = if (p(HartPrefixKey)) {
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@hcook hcook May 4, 2020 •
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If possible, I would put this in the trait HasTiles or HasRocketTiles, both of which actually currently get reused across multiple BaseSubsystem subclasses, unlike RocketSubsystem which is only used here and in soc-testsocket-sifive

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I would do that, but then this PR would break those other subclasses. Since the hartReg() part of this is needed to unblock the pipeline, I think I will do that refactor as a follow-up PR.

Some(BundleBroadcast[UInt](registered = true))
} else {
None
}

val hartPrefixes = hartPrefixNode.map { hpn => Seq.fill(tiles.size) {
val hps = BundleBridgeSink[UInt]
hps := hpn
hps
} }.getOrElse(Nil)

override lazy val module = new RocketSubsystemModuleImp(this)
}

class RocketSubsystemModuleImp[+L <: RocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasResetVectorWire
with HasRocketTilesModuleImp {
tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
wire.hartid := UInt(i)

for (i <- 0 until outer.tiles.size) {
val wire = tile_inputs(i)
val prefix = outer.hartPrefixes.lift(i).map(_.bundle).getOrElse(UInt(0))
wire.hartid := prefix | UInt(outer.hartIdList(i))
wire.reset_vector := global_reset_vector
}
}
10 changes: 6 additions & 4 deletions src/main/scala/tile/RocketTile.scala
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Expand Up @@ -11,7 +11,7 @@ import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{DCacheLogicalTree
import freechips.rocketchip.interrupts._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket._
import freechips.rocketchip.subsystem.{SubsystemResetSchemeKey, ResetSynchronous, RocketCrossingParams}
import freechips.rocketchip.subsystem.{SubsystemResetSchemeKey, ResetSynchronous, RocketCrossingParams, HartPrefixKey}
import freechips.rocketchip.util._

case class RocketTileParams(
Expand Down Expand Up @@ -156,11 +156,13 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
outer.traceSourceNode.bundle <> core.io.trace
core.io.traceStall := outer.traceAuxSinkNode.bundle.stall
outer.bpwatchSourceNode.bundle <> core.io.bpwatch
core.io.hartid := RegNext(constants.hartid)
outer.dcache.module.io.hartid := RegNext(constants.hartid)
outer.frontend.module.io.hartid := RegNext(constants.hartid)
outer.frontend.module.io.reset_vector := constants.reset_vector

def regHart(x: UInt): UInt = if (p(HartPrefixKey)) RegNext(x) else x
core.io.hartid := regHart(constants.hartid)
outer.dcache.module.io.hartid := regHart(constants.hartid)
outer.frontend.module.io.hartid := regHart(constants.hartid)

// Connect the core pipeline to other intra-tile modules
outer.frontend.module.io.cpu <> core.io.imem
dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
Expand Down