BundleMap: improved API for user bits

src/main/scala/amba/axis/Buffer.scala

@@ -14,7 +14,7 @@ class AXISBuffer(val params: BufferParams)(implicit p: Parameters) extends LazyM
   val node = AXISAdapterNode()
   lazy val module = new LazyModuleImp(this) {
     (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
-      out :<> params.irrevocable(in)
+      out :<>: params.irrevocable(in)
     }
   }
 }

src/main/scala/amba/axis/Bundles.scala

@@ -6,12 +6,22 @@ import chisel3.util._
 import freechips.rocketchip.util._
 
 sealed trait AXISKey
-case object AXISLast extends ControlKey[Bool]("last", _ := true.B) with AXISKey
-case object AXISId   extends ControlKey[UInt]("id",   _ := 0.U)    with AXISKey
-case object AXISDest extends ControlKey[UInt]("dest", _ := 0.U)    with AXISKey
-case object AXISKeep extends DataKey   [UInt]("keep", _ := ~0.U)   with AXISKey
-case object AXISStrb extends DataKey   [UInt]("strb", _ := ~0.U)   with AXISKey
-case object AXISData extends DataKey   [UInt]("data", _ := 0.U)    with AXISKey
+case object AXISLast extends ControlKey[Bool]("last") with AXISKey
+case object AXISId   extends ControlKey[UInt]("id")   with AXISKey
+case object AXISDest extends ControlKey[UInt]("dest") with AXISKey
+case object AXISKeep extends DataKey   [UInt]("keep") with AXISKey
+case object AXISStrb extends DataKey   [UInt]("strb") with AXISKey
+case object AXISData extends DataKey   [UInt]("data") with AXISKey
+
+case class AXISLastField()           extends SimpleBundleField(AXISLast)(Output(Bool()),        true.B)
+case class AXISIdField  (width: Int) extends SimpleBundleField(AXISId)  (Output(UInt(width.W)), 0.U)
+case class AXISDestField(width: Int) extends SimpleBundleField(AXISDest)(Output(UInt(width.W)), 0.U)
+case class AXISKeepField(width: Int) extends SimpleBundleField(AXISKeep)(Output(UInt(width.W)), ~0.U(width.W))
+case class AXISStrbField(width: Int) extends SimpleBundleField(AXISStrb)(Output(UInt(width.W)), ~0.U(width.W))
+case class AXISDataField(width: Int) extends BundleField(AXISData) {
+  def data = Output(UInt(width.W))
+  def default(x: UInt) { x := DontCare }
+}
 
 class AXISBundleBits(val params: AXISBundleParameters) extends BundleMap(AXISBundle.keys(params)) {
   override def cloneType: this.type = (new AXISBundleBits(params)).asInstanceOf[this.type]
@@ -30,13 +40,13 @@ class AXISBundle(val params: AXISBundleParameters) extends IrrevocableIO(new AXI
 object AXISBundle {
   def apply(params: AXISBundleParameters) = new AXISBundle(params)
   def standardKeys(params: AXISBundleParameters) = {
-    def maybe(b: Boolean, x: BundleField): Seq[BundleField] = if (b) List(x) else Nil
-    maybe(params.hasLast, AXISLast(Bool()))                  ++
-    maybe(params.hasId,   AXISId  (UInt(params.idBits  .W))) ++
-    maybe(params.hasDest, AXISDest(UInt(params.destBits.W))) ++
-    maybe(params.hasKeep, AXISKeep(UInt(params.keepBits.W))) ++
-    maybe(params.hasStrb, AXISStrb(UInt(params.strbBits.W))) ++
-    maybe(params.hasData, AXISData(UInt(params.dataBits.W)))
+    def maybe(b: Boolean, x: BundleFieldBase): Seq[BundleFieldBase] = if (b) List(x) else Nil
+    maybe(params.hasLast, AXISLastField())                ++
+    maybe(params.hasId,   AXISIdField  (params.idBits  )) ++
+    maybe(params.hasDest, AXISDestField(params.destBits)) ++
+    maybe(params.hasKeep, AXISKeepField(params.keepBits)) ++
+    maybe(params.hasStrb, AXISStrbField(params.strbBits)) ++
+    maybe(params.hasData, AXISDataField(params.dataBits))
   }
   def keys(params: AXISBundleParameters) =
     standardKeys(params) ++ params.userFields

src/main/scala/amba/axis/Parameters.scala

@@ -5,7 +5,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.internal.sourceinfo.SourceInfo
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.util.BundleField
+import freechips.rocketchip.util._
 import freechips.rocketchip.diplomacy._
 
 class AXISSlaveParameters private (
@@ -132,7 +132,7 @@ object AXISMasterParameters {
 
 class AXISMasterPortParameters private (
   val masters:      Seq[AXISMasterParameters],
-  val userFields:   Seq[BundleField],
+  val userFields:   Seq[BundleFieldBase],
   val isAligned:    Boolean, /* there are no 'Position byte's in transfers */
   val isContinuous: Boolean, /* there are no 'Null byte's except at the end of a transfer */
   val beatBytes:    Option[Int])
@@ -145,7 +145,7 @@ class AXISMasterPortParameters private (
 
   def v1copy(
     masters:      Seq[AXISMasterParameters] = masters,
-    userFields:   Seq[BundleField]          = userFields,
+    userFields:   Seq[BundleFieldBase]      = userFields,
     isAligned:    Boolean                   = isAligned,
     isContinuous: Boolean                   = isContinuous,
     beatBytes:    Option[Int]               = beatBytes) =
@@ -162,10 +162,10 @@ class AXISMasterPortParameters private (
 object AXISMasterPortParameters {
   def v1(
     masters:      Seq[AXISMasterParameters],
-    userFields:   Seq[BundleField] = Nil,
-    isAligned:    Boolean          = false,
-    isContinuous: Boolean          = false,
-    beatBytes:    Option[Int]      = None) =
+    userFields:   Seq[BundleFieldBase] = Nil,
+    isAligned:    Boolean              = false,
+    isContinuous: Boolean              = false,
+    beatBytes:    Option[Int]          = None) =
   {
     new AXISMasterPortParameters(
       masters      = masters,
@@ -180,7 +180,7 @@ class AXISBundleParameters private (
   val idBits:      Int,
   val destBits:    Int,
   val dataBits:    Int,
-  val userFields:  Seq[BundleField],
+  val userFields:  Seq[BundleFieldBase],
   val oneBeat:     Boolean,
   val aligned:     Boolean)
 {
@@ -203,17 +203,17 @@ class AXISBundleParameters private (
     idBits      = idBits   max x.idBits,
     destBits    = destBits max x.destBits,
     dataBits    = dataBits max x.dataBits,
-    userFields  = (userFields ++ x.userFields).distinct,
+    userFields  = BundleField.union(userFields ++ x.userFields),
     oneBeat     = oneBeat && x.oneBeat,
     aligned     = aligned && x.aligned)
 
   def v1copy(
-    idBits:      Int              = idBits,
-    destBits:    Int              = destBits,
-    dataBits:    Int              = dataBits,
-    userFields:  Seq[BundleField] = userFields,
-    oneBeat:     Boolean          = oneBeat,
-    aligned:     Boolean          = aligned) =
+    idBits:      Int = idBits,
+    destBits:    Int = destBits,
+    dataBits:    Int = dataBits,
+    userFields:  Seq[BundleFieldBase] = userFields,
+    oneBeat:     Boolean = oneBeat,
+    aligned:     Boolean = aligned) =
   {
     new AXISBundleParameters(
       idBits     = idBits,
@@ -239,7 +239,7 @@ object AXISBundleParameters {
     idBits:      Int,
     destBits:    Int,
     dataBits:    Int,
-    userFields:  Seq[BundleField],
+    userFields:  Seq[BundleFieldBase],
     oneBeat:     Boolean,
     aligned:     Boolean) =
   {

src/main/scala/amba/axis/Xbar.scala

@@ -41,28 +41,15 @@ class AXISXbar(beatBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin)(
     // Transform input bundle sources (dest uses global namespace on both sides)
     val in = Wire(Vec(io_in.size, AXISBundle(wide_bundle)))
     for (i <- 0 until in.size) {
-      io_in(i).ready := in(i).ready
-      in(i).valid    := io_in(i).valid
-
-      (in(i).bits assignL io_in(i).bits) foreach {
-        // Assign the potentially widened AXI-ID
-        case AXISId => if (in(i).bits.params.hasId) { in(i).bits.id := io_in(i).bits.id | inputIdRanges(i).start.U }
-        // All other fields should remain the same
-        case key => in(i).bits(key) :<= io_in(i).bits(key)
-      }
+      in(i) :<> io_in(i)
+      in(i).bits.lift(AXISId) foreach { _ := io_in(i).bits.id | inputIdRanges(i).start.U }
     }
 
     // Transform output bundle sinks (id use global namespace on both sides)
     val out = Wire(Vec(io_out.size, AXISBundle(wide_bundle)))
     for (o <- 0 until out.size) {
-      out(o).ready        := io_out(o).ready
-      io_out(o).valid     := out(o).valid
-      (io_out(o).bits assignL out(o).bits) foreach {
-        // Simplify the potentially narrowed AXI-Dest
-        case AXISDest => if (io_out(o).params.hasDest) { io_out(o).bits.dest := trim(out(o).bits.dest, outputIdRanges(o).size) }
-        // All other fields should remain the same
-        case key => io_out(o).bits(key) :<= out(o).bits(key)
-      }
+      io_out(o) :<> out(o)
+      io_out(o).bits.lift(AXISDest) foreach { _ := trim(out(o).bits.dest, outputIdRanges(o).size) }
     }
 
     // Fanout the input sources to the output sinks

src/main/scala/amba/package.scala

@@ -0,0 +1,30 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip
+
+import chisel3._
+import freechips.rocketchip.util._
+
+package object amba {
+  class AMBAProtBundle extends Bundle {
+    val cacheable  = Bool() // false => no need to probe other cores
+    val bufferable = Bool() // writeback caching ok?
+    val modifiable = Bool() // legal to read/write-combine/expand this request?
+    val privileged = Bool() // machine_mode=true,   user_mode=false
+    val secure     = Bool() // secure_master=true,  normal=false
+    val fetch      = Bool() // instruct_fetch=true, load/store=false
+  }
+
+  case object AMBAProt extends ControlKey[AMBAProtBundle]("amba_prot")
+  case class AMBAProtField() extends BundleField(AMBAProt) {
+    def data = Output(new AMBAProtBundle)
+    def default(x: AMBAProtBundle) {
+      x.cacheable  := true.B
+      x.bufferable := true.B
+      x.modifiable := true.B
+      x.privileged := false.B
+      x.secure     := false.B
+      x.fetch      := false.B
+    }
+  }
+}