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Debug APB: Prevent aliasing on undefined addresses #2213

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Dec 2, 2019
Merged

Debug APB: Prevent aliasing on undefined addresses #2213

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9 changes: 8 additions & 1 deletion src/main/scala/devices/debug/APB.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,15 @@ import freechips.rocketchip.amba.apb.{APBRegisterNode}

case object APBDebugRegistersKey extends Field[Map[Int, Seq[RegField]]](Map())

object APBDebugConsts {
def apbDebugRegBase = 0xF00
def apbDebugRegSize = 0x100
}

class APBDebugRegisters()(implicit p: Parameters) extends LazyModule {

val node = APBRegisterNode(
address = AddressSet(base=0xF00, mask=0xFF),
address = AddressSet(base=APBDebugConsts.apbDebugRegBase, mask=APBDebugConsts.apbDebugRegSize-1),
beatBytes = 4,
executable = false
)
Expand All @@ -23,3 +28,5 @@ class APBDebugRegisters()(implicit p: Parameters) extends LazyModule {

}
}


18 changes: 14 additions & 4 deletions src/main/scala/devices/debug/Debug.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ import freechips.rocketchip.regmapper._
import freechips.rocketchip.rocket.Instructions
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
Expand Down Expand Up @@ -594,6 +595,8 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod

class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule {

val cfg = p(DebugModuleKey).get

val dmiXbar = LazyModule (new TLXbar())

val dmi2tlOpt = (!p(ExportDebug).apb).option({
Expand All @@ -605,14 +608,18 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
val apbNodeOpt = p(ExportDebug).apb.option({
val apb2tl = LazyModule(new APBToTL())
val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr),
maxAtomic=0, maxTransfer=4)
val tlError = LazyModule(new TLError(tlErrorParams))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())

apbRegs.node := apbXbar.node
apb2tl.node := apbXbar.node
apb2tlBuffer.node := apb2tl.node
dmiXbar.node := apb2tlBuffer.node

tlError.node := dmiXbar.node
apbXbar.node
})

Expand Down Expand Up @@ -643,6 +650,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
dmOuter.module.io.hgDebugInt := io.hgDebugInt
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}}

}
}

Expand All @@ -655,11 +663,13 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
val cfg = p(DebugModuleKey).get
def getCfg = () => cfg

val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2

val dmiNode = TLRegisterNode(
// Address is range 0 to 0x1FF except DMCONTROL, HAWINDOWSEL, HAWINDOW which are handled by Outer
address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (0x200 - ((DMI_HAWINDOW + 1) << 2))),
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),
device = device,
beatBytes = 4,
executable = false
Expand Down