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Restoring staged generator PRs (Reverting #2329)
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,52 @@ | ||
| // See LICENSE.SiFive for license details. | ||
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| package freechips.rocketchip.stage | ||
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| import chisel3.experimental.BaseModule | ||
| import firrtl.annotations.{Annotation, NoTargetAnnotation} | ||
| import firrtl.options.{HasShellOptions, ShellOption, Unserializable} | ||
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| sealed trait RocketChipOption extends Unserializable { this: Annotation => } | ||
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| /* required options */ | ||
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| /** Path to top module class */ | ||
| case class TopModuleAnnotation(clazz: Class[_ <: Any]) extends NoTargetAnnotation with RocketChipOption | ||
| private[stage] object TopModuleAnnotation extends HasShellOptions { | ||
| override val options = Seq( | ||
| new ShellOption[String]( | ||
| longOption = "top-module", | ||
| toAnnotationSeq = a => Seq(TopModuleAnnotation(Class.forName(a).asInstanceOf[Class[_ <: BaseModule]])), | ||
| helpText = "<top module>", | ||
| shortOption = Some("T") | ||
| ) | ||
| ) | ||
| } | ||
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| /** Paths to config classes */ | ||
| case class ConfigsAnnotation(configNames: Seq[String]) extends NoTargetAnnotation with RocketChipOption | ||
| private[stage] object ConfigsAnnotation extends HasShellOptions { | ||
| override val options = Seq( | ||
| new ShellOption[Seq[String]]( | ||
| longOption = "configs", | ||
| toAnnotationSeq = a => Seq(ConfigsAnnotation(a)), | ||
| helpText = "<comma-delimited configs>", | ||
| shortOption = Some("C") | ||
| ) | ||
| ) | ||
| } | ||
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| /* optional options */ | ||
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| /** Optional base name for generated files' filenames */ | ||
| case class OutputBaseNameAnnotation(outputBaseName: String) extends NoTargetAnnotation with RocketChipOption | ||
| private[stage] object OutputBaseNameAnnotation extends HasShellOptions { | ||
| override val options = Seq( | ||
| new ShellOption[String]( | ||
| longOption = "name", | ||
| toAnnotationSeq = a => Seq(OutputBaseNameAnnotation(a)), | ||
| helpText = "<base name of output files>", | ||
| shortOption = Some("n") | ||
| ) | ||
| ) | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,17 @@ | ||
| // See LICENSE.SiFive for license details. | ||
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| package freechips.rocketchip.stage | ||
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| import firrtl.options.Shell | ||
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| trait RocketChipCli { this: Shell => | ||
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| parser.note("Rocket Chip Compiler Options") | ||
| Seq( | ||
| TopModuleAnnotation, | ||
| ConfigsAnnotation, | ||
| OutputBaseNameAnnotation, | ||
| ) | ||
| .foreach(_.addOptions(parser)) | ||
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| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,41 @@ | ||
| // See LICENSE.SiFive for license details. | ||
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| package freechips.rocketchip.stage | ||
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| class RocketChipOptions private[stage] ( | ||
| val topModule: Option[Class[_ <: Any]] = None, | ||
| val configNames: Option[Seq[String]] = None, | ||
| val outputBaseName: Option[String] = None) { | ||
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| private[stage] def copy( | ||
| topModule: Option[Class[_ <: Any]] = topModule, | ||
| configNames: Option[Seq[String]] = configNames, | ||
| outputBaseName: Option[String] = outputBaseName, | ||
| ): RocketChipOptions = { | ||
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| new RocketChipOptions( | ||
| topModule=topModule, | ||
| configNames=configNames, | ||
| outputBaseName=outputBaseName, | ||
| ) | ||
| } | ||
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| lazy val topPackage: Option[String] = topModule match { | ||
| case Some(a) => Some(a.getPackage.getName) | ||
| case _ => None | ||
| } | ||
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| lazy val configClass: Option[String] = configNames match { | ||
| case Some(names) => | ||
| val classNames = names.map{ n => n.split('.').last } | ||
| Some(classNames.mkString("_")) | ||
| case _ => None | ||
| } | ||
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| lazy val longName: Option[String] = outputBaseName match { | ||
| case Some(name) => Some(name) | ||
| case _ => | ||
| if (!topPackage.isEmpty && !configClass.isEmpty) Some(s"${topPackage.get}.${configClass.get}") else None | ||
| } | ||
| } | ||
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