Merge pull request #2424 from chipsalliance/stage-ordering-fixes

A Pair of Phase-Ordering Fixes
chipsalliance · Apr 20, 2020 · 3f7074f · 3f7074f
2 parents 4689a06 + b9f4a5a
commit 3f7074f
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Showing 2 changed files with 3 additions and 4 deletions.
diff --git a/src/main/scala/stage/phases/AddDefaultTests.scala b/src/main/scala/stage/phases/AddDefaultTests.scala
@@ -7,7 +7,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3.stage.phases.Elaborate
 import firrtl.AnnotationSeq
 import firrtl.annotations.NoTargetAnnotation
-import firrtl.options.{Phase, PreservesAll}
+import firrtl.options.{Phase, PreservesAll, Unserializable}
 import firrtl.options.Viewer.view
 import freechips.rocketchip.stage.RocketChipOptions
 import freechips.rocketchip.subsystem.RocketTilesKey
@@ -19,7 +19,7 @@ import freechips.rocketchip.system.DefaultTestSuites._
 import scala.collection.mutable
 
 /** Annotation that contains a list of [[RocketTestSuite]]s to run */
-case class RocketTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation
+case class RocketTestSuiteAnnotation(tests: Seq[RocketTestSuite]) extends NoTargetAnnotation with Unserializable
 
 /** Generates [[RocketTestSuiteAnnotation]] depending on whether the top-module project is part of
  *  [[freechips.rocketchip.system]] or not (e.g. for unit tests).

diff --git a/src/main/scala/stage/phases/TransformAnnotations.scala b/src/main/scala/stage/phases/TransformAnnotations.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.stage.phases
 
 import chisel3.stage.ChiselOutputFileAnnotation
-import chisel3.stage.phases.Emitter
 import firrtl.AnnotationSeq
 import firrtl.options.Viewer.view
 import firrtl.options.{Phase, PreservesAll}
@@ -14,7 +13,7 @@ import freechips.rocketchip.util.HasRocketChipStageUtils
 class TransformAnnotations extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
 
   override val prerequisites = Seq(classOf[Checks])
-  override val dependents = Seq(classOf[Emitter])
+  override val dependents = Seq(classOf[chisel3.stage.phases.AddImplicitOutputFile])
 
   override def transform(annotations: AnnotationSeq): AnnotationSeq = {
     /** Construct output file annotation for emission */