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Remove circt.Intrinsic annotation. #3945

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2 changes: 0 additions & 2 deletions src/main/scala/chisel3/util/circt/ClockGate.scala
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@ import chisel3._
import chisel3.experimental.IntrinsicModule
import chisel3.internal.Builder

import circt.Intrinsic

/** A clock gate intrinsic.
*/
private class ClockGateIntrinsic extends IntrinsicModule("circt_clock_gate") {
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2 changes: 0 additions & 2 deletions src/main/scala/chisel3/util/circt/IsX.scala
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@ import chisel3._
import chisel3.experimental.IntrinsicModule
import chisel3.internal.Builder

import circt.Intrinsic

/** Create a module with a parameterized type which returns whether the input
* is a verilog 'x'.
*/
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2 changes: 0 additions & 2 deletions src/main/scala/chisel3/util/circt/LTLIntrinsics.scala
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@ import chisel3._
import chisel3.experimental.{IntParam, IntrinsicModule, Param, StringParam}
import chisel3.experimental.hierarchy.{instantiable, public}

import circt.Intrinsic

private object Utils {
private[chisel3] def withoutNone(params: Map[String, Option[Param]]): Map[String, Param] =
params.collect { case (name, Some(param)) => (name, param) }
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2 changes: 0 additions & 2 deletions src/main/scala/chisel3/util/circt/PlusArgsTest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@ import chisel3._
import chisel3.experimental.IntrinsicModule
import chisel3.internal.Builder

import circt.Intrinsic

/** Create a module with a parameterized type which calls the verilog function
* \$test\$plusargs to test for the existence of the string str in the
* simulator command line.
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2 changes: 0 additions & 2 deletions src/main/scala/chisel3/util/circt/PlusArgsValue.scala
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,6 @@ import chisel3._
import chisel3.experimental.IntrinsicModule
import chisel3.internal.Builder

import circt.Intrinsic

/** Create a module which generates a verilog \$value\$plusargs. This returns a
* value as indicated by the format string and a flag for whether the value
* was found.
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2 changes: 0 additions & 2 deletions src/main/scala/chisel3/util/circt/Synthesis.scala
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,6 @@ import chisel3._
import chisel3.experimental.{requireIsHardware, IntrinsicModule}
import chisel3.internal.Builder

import circt.Intrinsic

/** A 2-to-1 mux cell intrinsic.
*/
private class Mux2CellIntrinsic[T <: Data](gen: T) extends IntrinsicModule("circt_mux2cell") {
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14 changes: 0 additions & 14 deletions src/main/scala/circt/Intrinisic.scala

This file was deleted.

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