[SVSim] Fixed non-firing AssertProperty in SVSim (#4087)

(cherry picked from commit d3ab477)

src/test/scala/chiselTests/LTLSpec.scala

@@ -6,13 +6,14 @@ import chisel3._
 import chisel3.ltl._
 import chisel3.testers.BasicTester
 import _root_.circt.stage.ChiselStage
+import chiselTests.ChiselRunners
 
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
 import Sequence._
 
-class LTLSpec extends AnyFlatSpec with Matchers {
+class LTLSpec extends AnyFlatSpec with Matchers with ChiselRunners {
   it should "allow booleans to be used as sequences" in {
     val chirrtl = ChiselStage.emitCHIRRTL(new RawModule {
       val a = IO(Input(Bool()))
@@ -336,4 +337,12 @@ class LTLSpec extends AnyFlatSpec with Matchers {
     chirrtl should include("connect ltl_concat_4.rhs, ltl_delay_4")
     chirrtl should include("connect verif_6.property, ltl_concat_4.out")
   }
+
+  it should "fail correctly in verilator simulation" in {
+    assertTesterFails(new BasicTester {
+      withClockAndReset(clock, reset) {
+        AssertProperty(0.U === 1.U)
+      }
+    })
+  }
 }

svsim/src/main/scala/verilator/Backend.scala

@@ -58,6 +58,7 @@ final class Backend(
             "-o", s"../$outputBinaryName", // "Name of final executable"
             "--top-module", topModuleName, // "Name of top-level input module"
             "--Mdir", "verilated-sources",  // "Name of output object directory"
+            "--assert", // Enable assertions 
           ),
 
           commonSettings.libraryExtensions match {