Additional round of lint cleanup

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-6cd6271af5cc73b4c69623c0fb3354d0d211b459c36b1c0820075afadd8ce3eda9f3f4c0e50ae2f8b96f2e74b837f94b
+2feeef5876321043dcbc1134f4143038d5c6b0588afbc56a44f3886ee264908e10650c88c85aa2e9e0ba9b6e8969be99

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1714005956
+1714158756

src/aes/config/compile.yml

@@ -39,3 +39,7 @@ targets:
       - $COMPILE_ROOT/rtl/aes_prng_masking.sv
       - $COMPILE_ROOT/rtl/aes_key_expand.sv
     tops: [aes_cipher_core]
+  rtl_lint:
+    directories: []
+    waiver_files: []
+    tops: [aes_cipher_core]

src/aes/rtl/aes_pkg.sv

@@ -68,7 +68,7 @@ parameter masking_lfsr_perm_t RndCnstMaskingLfsrPermDefault = {
   256'h808d419d63982a16995e0e3b57826a36718a9329452492533d83115a75316e15
 };
 
-typedef enum integer {
+typedef enum logic [31:0] {
   SBoxImplLut,                   // Unmasked LUT-based S-Box
   SBoxImplCanright,              // Unmasked Canright S-Box, see aes_sbox_canright.sv
   SBoxImplCanrightMasked,        // First-order masked Canright S-Box

src/aes/rtl/aes_reg_pkg.sv

@@ -336,7 +336,7 @@ package aes_reg_pkg;
   parameter logic [0:0] AES_CTRL_SHADOWED_MANUAL_OPERATION_RESVAL = 1'h 0;
 
   // Register index
-  typedef enum int {
+  typedef enum logic [31:0] {
     AES_ALERT_TEST,
     AES_KEY_SHARE0_0,
     AES_KEY_SHARE0_1,

src/caliptra_prim/rtl/caliptra_prim_packer_fifo.sv

@@ -132,7 +132,7 @@ module caliptra_prim_packer_fifo #(
 
     assign lsb_is_one = {{DepthW{1'b0}},1'b1};
     assign max_value = FullDepth;
-    assign rdata_shifted = data_q >> ptr_q*OutW;
+    assign rdata_shifted = MaxW'(data_q >> ptr_q*OutW);
     assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q;
     assign clear_data = (ClearOnRead && clear_status) || clr_q;
     assign load_data = wvalid_i && wready_o;

src/caliptra_prim/rtl/caliptra_prim_pkg.sv

@@ -9,7 +9,7 @@
 package caliptra_prim_pkg;
 
   // Implementation target specialization
-  typedef enum integer {
+  typedef enum logic [31:0] {
     ImplGeneric,
     ImplXilinx,
     ImplBadbit

src/caliptra_prim/rtl/caliptra_prim_util_pkg.sv

@@ -25,17 +25,19 @@ package caliptra_prim_util_pkg;
    *   vector value. The argument shall be treated as an unsigned
    *   value, and an argument value of 0 shall produce a result of 0.
    */
-  function automatic integer _clog2(integer value);
-    integer result;
-    // Use an intermediate value to avoid assigning to an input port, which produces a warning in
-    // Synopsys DC.
-    integer v = value;
-    v = v - 1;
-    for (result = 0; v > 0; result++) begin
-      v = v >> 1;
-    end
-    return result;
-  endfunction
+
+  //Function causing LINT errors. Not used in current codebase
+  //deprecated and replaced by $clog2() //function automatic integer _clog2(integer value);
+  //deprecated and replaced by $clog2() //  integer result;
+  //deprecated and replaced by $clog2() // Use an intermediate value to avoid assigning to an input port, which produces a warning in
+  //deprecated and replaced by $clog2() // Synopsys DC.
+  //deprecated and replaced by $clog2() //  integer v = value;
+  //deprecated and replaced by $clog2() //  v = v - 1;
+  //deprecated and replaced by $clog2() //  for (result = 0; v > 0; result++) begin
+  //deprecated and replaced by $clog2() //    v = v >> 1;
+  //deprecated and replaced by $clog2() //  end
+  //deprecated and replaced by $clog2() //  return result;
+  //deprecated and replaced by $clog2() //endfunction
 
 
   /**

src/csrng/config/compile.yml

@@ -41,6 +41,11 @@ targets:
       - $COMPILE_ROOT/rtl/csrng_cmd_stage.sv
       - $COMPILE_ROOT/rtl/csrng.sv
     tops: [csrng]
+  rtl_lint:
+    directories: []
+    waiver_files:
+      - $MSFT_REPO_ROOT/src/csrng/config/design_lint/sglint_waivers
+    tops: [csrng]
 ---
 provides: [csrng_tb]
 schema_version: 2.4.0

src/csrng/rtl/csrng.sv

@@ -15,7 +15,7 @@ module csrng
 #(
   parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplCanright,
   parameter logic [csrng_reg_pkg::NumAlerts-1:0] AlertAsyncOn = {csrng_reg_pkg::NumAlerts{1'b1}},
-  parameter int NHwApps = 2,
+  parameter logic [31:0] NHwApps = 2,
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0),
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0),
   parameter AHBDataWidth = 64,

src/csrng/rtl/csrng_block_encrypt.sv

@@ -7,10 +7,10 @@
 
 module csrng_block_encrypt import csrng_pkg::*; #(
   parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut,
-  parameter int Cmd = 3,
-  parameter int StateId = 4,
-  parameter int BlkLen = 128,
-  parameter int KeyLen = 256
+  parameter logic [31:0] Cmd = 3,
+  parameter logic [31:0] StateId = 4,
+  parameter logic [31:0] BlkLen = 128,
+  parameter logic [31:0] KeyLen = 256
 ) (
   input logic                clk_i,
   input logic                rst_ni,
@@ -33,9 +33,9 @@ module csrng_block_encrypt import csrng_pkg::*; #(
   output logic [2:0]         block_encrypt_sfifo_blkenc_err_o
 );
 
-  localparam int BlkEncFifoDepth = 1;
-  localparam int BlkEncFifoWidth = StateId+Cmd;
-  localparam int NumShares = 1;
+  localparam logic[31:0] BlkEncFifoDepth = 1;
+  localparam logic[31:0] BlkEncFifoWidth = StateId+Cmd;
+  localparam logic[31:0] NumShares = 1;
 
   // signals
   // blk_encrypt_in fifo

src/csrng/rtl/csrng_cmd_stage.sv

@@ -6,9 +6,9 @@
 //
 
 module csrng_cmd_stage import csrng_pkg::*; #(
-  parameter int CmdFifoWidth = 32,
-  parameter int CmdFifoDepth = 16,
-  parameter int StateId = 4
+  parameter logic [31:0] CmdFifoWidth = 32,
+  parameter logic [31:0] CmdFifoDepth = 16,
+  parameter logic [31:0] StateId = 4
 ) (
   input logic                        clk_i,
   input logic                        rst_ni,
@@ -48,9 +48,9 @@ module csrng_cmd_stage import csrng_pkg::*; #(
 );
 
   // Genbits parameters.
-  localparam int GenBitsFifoWidth = 1+128;
-  localparam int GenBitsFifoDepth = 1;
-  localparam int GenBitsCntrWidth = 13;
+  localparam logic[31:0] GenBitsFifoWidth = 1+128;
+  localparam logic[31:0] GenBitsFifoDepth = 1;
+  localparam logic[31:0] GenBitsCntrWidth = 13;
 
   // Command FIFO.
   logic [CmdFifoWidth-1:0] sfifo_cmd_rdata;
@@ -191,7 +191,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
     .set_cnt_i(sfifo_cmd_rdata[24:12]),
     .incr_en_i(1'b0),
     .decr_en_i(cmd_gen_cnt_dec), // Count down.
-    .step_i(GenBitsCntrWidth'(1)),
+    .step_i(GenBitsCntrWidth'(unsigned'(1))),
     .cnt_o(cmd_gen_cnt),
     .cnt_next_o(),
     .err_o(cmd_gen_cnt_err_o)
@@ -224,7 +224,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
   // Minimum Hamming weight: 1
   // Maximum Hamming weight: 7
   //
-  localparam int StateWidth = 8;
+  localparam logic[31:0] StateWidth = 8;
   typedef    enum logic [StateWidth-1:0] {
     Idle      = 8'b00011011, // idle
     ArbGnt    = 8'b11110101, // general arbiter request
@@ -285,7 +285,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
           cmd_gen_1st_req = 1'b1;
           cmd_arb_sop_o = 1'b1;
           cmd_fifo_pop = 1'b1;
-          if (sfifo_cmd_rdata[24:12] == GenBitsCntrWidth'(1)) begin
+          if (sfifo_cmd_rdata[24:12] == GenBitsCntrWidth'(unsigned'(1))) begin
             cmd_gen_cnt_last = 1'b1;
           end
           if (cmd_len == '0) begin
@@ -350,7 +350,7 @@ module csrng_cmd_stage import csrng_pkg::*; #(
           cmd_gen_inc_req = 1'b1;
           state_d = GenCmdChk;
           // Check for final genbits beat.
-          if (cmd_gen_cnt == GenBitsCntrWidth'(1)) begin
+          if (cmd_gen_cnt == GenBitsCntrWidth'(unsigned'(1))) begin
             cmd_gen_cnt_last = 1'b1;
           end
         end

src/csrng/rtl/csrng_core.sv

@@ -13,7 +13,7 @@ module csrng_core
  import lc_ctrl_pkg::*;
 #(
   parameter aes_pkg::sbox_impl_e SBoxImpl = aes_pkg::SBoxImplLut,
-  parameter int NHwApps = 2,
+  parameter logic [31:0] NHwApps = 2,
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivNonProduction = CsKeymgrDivWidth'(0),
   parameter cs_keymgr_div_t RndCnstCsKeymgrDivProduction = CsKeymgrDivWidth'(0)
 ) (
@@ -60,26 +60,26 @@ module csrng_core
   import caliptra_prim_mubi_pkg::mubi4_test_true_strict;
   import caliptra_prim_mubi_pkg::mubi4_test_invalid;
 
-  localparam int NApps = NHwApps + 1;
-  localparam int AppCmdWidth = 32;
-  localparam int AppCmdFifoDepth = 2;
-  localparam int GenBitsWidth = 128;
-  localparam int Cmd = 3;
-  localparam int StateId = 4;
-  localparam int KeyLen = 256;
-  localparam int BlkLen = 128;
-  localparam int SeedLen = 384;
-  localparam int CtrLen = 32;
-  localparam int NBlkEncArbReqs = 2;
-  localparam int BlkEncArbWidth = KeyLen+BlkLen+StateId+Cmd;
-  localparam int NUpdateArbReqs = 2;
-  localparam int UpdateArbWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd;
-  localparam int MaxClen = 12;
-  localparam int ADataDepthWidth = SeedLen/AppCmdWidth;
-  localparam unsigned ADataDepthClog = $clog2(ADataDepthWidth)+1;
-  localparam int CsEnableCopies = 53;
-  localparam int LcHwDebugCopies = 1;
-  localparam int Flag0Copies = 3;
+  localparam logic [31:0] NApps = NHwApps + 1;
+  localparam logic [31:0] AppCmdWidth = 32;
+  localparam logic [31:0] AppCmdFifoDepth = 2;
+  localparam logic [31:0] GenBitsWidth = 128;
+  localparam logic [31:0] Cmd = 3;
+  localparam logic [31:0] StateId = 4;
+  localparam logic [31:0] KeyLen = 256;
+  localparam logic [31:0] BlkLen = 128;
+  localparam logic [31:0] SeedLen = 384;
+  localparam logic [31:0] CtrLen = 32;
+  localparam logic [31:0] NBlkEncArbReqs = 2;
+  localparam logic [31:0] BlkEncArbWidth = KeyLen+BlkLen+StateId+Cmd;
+  localparam logic [31:0] NUpdateArbReqs = 2;
+  localparam logic [31:0] UpdateArbWidth = KeyLen+BlkLen+SeedLen+StateId+Cmd;
+  localparam logic [31:0] MaxClen = 12;
+  localparam logic [31:0] ADataDepthWidth = SeedLen/AppCmdWidth;
+  localparam logic [31:0] ADataDepthClog = $clog2(ADataDepthWidth)+1;
+  localparam logic [31:0] CsEnableCopies = 53;
+  localparam logic [31:0] LcHwDebugCopies = 1;
+  localparam logic [31:0] Flag0Copies = 3;
 
   // signals
   // interrupt signals

src/csrng/rtl/csrng_ctr_drbg_cmd.sv

@@ -7,12 +7,12 @@
 // Accepts all csrng commands
 
 module csrng_ctr_drbg_cmd import csrng_pkg::*; #(
-  parameter int Cmd = 3,
-  parameter int StateId = 4,
-  parameter int BlkLen = 128,
-  parameter int KeyLen = 256,
-  parameter int SeedLen = 384,
-  parameter int CtrLen  = 32
+  parameter logic [31:0] Cmd = 3,
+  parameter logic [31:0] StateId = 4,
+  parameter logic [31:0] BlkLen = 128,
+  parameter logic [31:0] KeyLen = 256,
+  parameter logic [31:0] SeedLen = 384,
+  parameter logic [31:0] CtrLen  = 32
 ) (
   input logic                clk_i,
   input logic                rst_ni,
@@ -65,12 +65,12 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #(
   output logic [2:0]         ctr_drbg_cmd_sfifo_keyvrc_err_o
 );
 
-  localparam int CmdreqFifoDepth = 1;
-  localparam int CmdreqFifoWidth = KeyLen+BlkLen+CtrLen+1+2*SeedLen+1+StateId+Cmd;
-  localparam int RCStageFifoDepth = 1;
-  localparam int RCStageFifoWidth = KeyLen+BlkLen+StateId+CtrLen+1+SeedLen+1+Cmd;
-  localparam int KeyVRCFifoDepth = 1;
-  localparam int KeyVRCFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd;
+  localparam logic[31:0] CmdreqFifoDepth = 1;
+  localparam logic[31:0] CmdreqFifoWidth = KeyLen+BlkLen+CtrLen+1+2*SeedLen+1+StateId+Cmd;
+  localparam logic[31:0] RCStageFifoDepth = 1;
+  localparam logic[31:0] RCStageFifoWidth = KeyLen+BlkLen+StateId+CtrLen+1+SeedLen+1+Cmd;
+  localparam logic[31:0] KeyVRCFifoDepth = 1;
+  localparam logic[31:0] KeyVRCFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd;
 
 
   // signals
@@ -319,7 +319,7 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; #(
   assign ctr_drbg_cmd_ack_o = sfifo_keyvrc_pop;
 
   assign ctr_drbg_cmd_sts_o = sfifo_keyvrc_pop && (ctr_drbg_cmd_ccmd_o == UNI) &&
-         ((KeyLen == '0) && (BlkLen == '0) && (CtrLen == '0));
+         ((KeyLen == unsigned'(0)) && (BlkLen == unsigned'(0)) && (CtrLen == unsigned'(0)));
 
 
 endmodule

src/csrng/rtl/csrng_ctr_drbg_gen.sv

@@ -9,13 +9,13 @@
 // ctr_drbg cmd module.
 
 module csrng_ctr_drbg_gen import csrng_pkg::*; #(
-  parameter int NApps = 4,
-  parameter int Cmd = 3,
-  parameter int StateId = 4,
-  parameter int BlkLen = 128,
-  parameter int KeyLen = 256,
-  parameter int SeedLen = 384,
-  parameter int CtrLen  = 32
+  parameter logic [31:0] NApps = 4,
+  parameter logic [31:0] Cmd = 3,
+  parameter logic [31:0] StateId = 4,
+  parameter logic [31:0] BlkLen = 128,
+  parameter logic [31:0] KeyLen = 256,
+  parameter logic [31:0] SeedLen = 384,
+  parameter logic [31:0] CtrLen  = 32
 ) (
   input logic                clk_i,
   input logic                rst_ni,
@@ -85,16 +85,16 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
   output logic               ctr_drbg_gen_sm_err_o
 );
 
-  localparam int GenreqFifoDepth = 1;
-  localparam int GenreqFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd;
-  localparam int BlkEncAckFifoDepth = 1;
-  localparam int BlkEncAckFifoWidth = BlkLen+StateId+Cmd;
-  localparam int AdstageFifoDepth = 1;
-  localparam int AdstageFifoWidth = KeyLen+BlkLen+CtrLen+1+1;
-  localparam int RCStageFifoDepth = 1;
-  localparam int RCStageFifoWidth = KeyLen+BlkLen+BlkLen+CtrLen+1+1+StateId+Cmd;
-  localparam int GenbitsFifoDepth = 1;
-  localparam int GenbitsFifoWidth = 1+BlkLen+KeyLen+BlkLen+CtrLen+StateId+Cmd;
+  localparam logic[31:0] GenreqFifoDepth = 1;
+  localparam logic[31:0] GenreqFifoWidth = KeyLen+BlkLen+CtrLen+1+SeedLen+1+StateId+Cmd;
+  localparam logic[31:0] BlkEncAckFifoDepth = 1;
+  localparam logic[31:0] BlkEncAckFifoWidth = BlkLen+StateId+Cmd;
+  localparam logic[31:0] AdstageFifoDepth = 1;
+  localparam logic[31:0] AdstageFifoWidth = KeyLen+BlkLen+CtrLen+1+1;
+  localparam logic[31:0] RCStageFifoDepth = 1;
+  localparam logic[31:0] RCStageFifoWidth = KeyLen+BlkLen+BlkLen+CtrLen+1+1+StateId+Cmd;
+  localparam logic[31:0] GenbitsFifoDepth = 1;
+  localparam logic[31:0] GenbitsFifoWidth = 1+BlkLen+KeyLen+BlkLen+CtrLen+StateId+Cmd;
 
   // signals
   logic [Cmd-1:0]     genreq_ccmd;
@@ -205,7 +205,7 @@ module csrng_ctr_drbg_gen import csrng_pkg::*; #(
 // Maximum Hamming weight: 3
 //
 
-  localparam int StateWidth = 5;
+  localparam logic[31:0] StateWidth = 5;
   typedef enum logic [StateWidth-1:0] {
     ReqIdle  = 5'b01101,
     ReqSend  = 5'b00011,