Releases: cescalara/zynq_ip_hls
Releases · cescalara/zynq_ip_hls
v1.3.0
Updates
Fix bug in trig_pixel output of L2 trigger
v1.1.0 Fix bug in trig_pixel output
Version 1 release: updates to L2 trigger
First version with all functionality included.
Major changes in L2 trigger:
- Add triggered pixel output (a number from 0 - 2303)
- Make the trigger threshold configurable (
N_BG
is the number of times above background level) - Make the lower limit of the threshold configurable (
LOW_THRESH
is the lowest allowed trigger threshold)
Inputs/outputs were implemented in the same way as previous IO (n_pixels in_bus
and trig_data
) to the trigger block.
The configurable parameters:
N_BG
is auint8_t
with ans_axilite
port bundled into theCTRL_BUS
LOW_THRESH
is auint32_t
with ans_axilite
port bundled into theCTRL_BUS
The output triggered pixel:
trig_pixel
is avolatile int *
with anap_ovld
port
Scurve adder IP is unchanged.
First stable release of IP implemented in the Zynq board
This is the L2 trigger and Scurve adder IP as used for testing during the March 2018 campaign in TurLab at the University of Turin.