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Releases: cescalara/zynq_ip_hls

v1.3.0

07 Feb 14:29
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Add double_trig output, hold 1st triggered trig_pixel abd update expo…

Updates

18 Apr 10:46
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Main changes:

  • added the double_trig output to check for simultaneous triggers
  • changed order of trigger decision so "first" (ie. first of the 2304 pixels in the AXI4 stream) pixel ID is held
  • updated the exported RTL

Fix bug in trig_pixel output of L2 trigger

18 Apr 09:12
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v1.1.0

Fix bug in trig_pixel output

Version 1 release: updates to L2 trigger

13 Apr 17:58
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First version with all functionality included.

Major changes in L2 trigger:

  • Add triggered pixel output (a number from 0 - 2303)
  • Make the trigger threshold configurable (N_BG is the number of times above background level)
  • Make the lower limit of the threshold configurable (LOW_THRESH is the lowest allowed trigger threshold)

Inputs/outputs were implemented in the same way as previous IO (n_pixels in_bus and trig_data) to the trigger block.

The configurable parameters:

  • N_BG is a uint8_t with an s_axilite port bundled into the CTRL_BUS
  • LOW_THRESH is a uint32_t with an s_axilite port bundled into the CTRL_BUS

The output triggered pixel:

  • trig_pixel is a volatile int * with an ap_ovld port

Scurve adder IP is unchanged.

First stable release of IP implemented in the Zynq board

13 Apr 14:45
66e66a6
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This is the L2 trigger and Scurve adder IP as used for testing during the March 2018 campaign in TurLab at the University of Turin.