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fuzzgen: Add SIMD instructions supported by the interpreter #5971
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Broken in the interpreter bytecodealliance#5911
Broken in the interpreter bytecodealliance#5915
This is broken in the interpreter bytecodealliance#5916
Turns out it doesen't exist
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jameysharp
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Hooray! Looks good overall. I just have a few small requests.
Co-Authored-By: Jamey Sharp <jsharp@fastly.com>
Co-Authored-By: Jamey Sharp <jsharp@fastly.com>
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…alliance#5971) * fuzzgen: Add some SIMD instructions * fuzzgen: Remove `scalar_to_vector` Broken in the interpreter bytecodealliance#5911 * fuzzgen: Remove SIMD bitcasts Broken in the interpreter bytecodealliance#5915 * fuzzgen: Fix insert lane * fuzzgen: Remove debug code * fuzzgen: Remove vall_true This is broken in the interpreter bytecodealliance#5916 * fuzzgen: Disable a few more ops * fuzzgen: Remove `iadd_pairwise.i64x2` Turns out it doesen't exist * fuzzgen: Remove scalar `sqmul_round_sat` bytecodealliance#5923 * fuzzgen: Disable aligned loads to SIMD values * fuzzgen: Address Review Feedback Co-Authored-By: Jamey Sharp <jsharp@fastly.com> * fuzzgen: Rework `cmp` exclusion rules Co-Authored-By: Jamey Sharp <jsharp@fastly.com> --------- Co-authored-by: Jamey Sharp <jsharp@fastly.com>
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👋 Hey,
This PR adds all SIMD instructions currently supported by the interpreter to the fuzzer. There is a surprising amount of missing coverage even with all of these ones (i.e. lots of work to do in the interpreter)!
I've also had to disable aligned loads/stores for > 8 bytes. It's really hard to do this without support from cranelift, and I think its probably best to go add support for that before re-enabling it here.
I gave this a bunch of fuzzing time, and it has stopped crashing on all arches. S390X was a little bit harder since I was only able to test it on QEMU and its quite a bit slower than native hardware though it ran about 12hours on 8 cores without crashing, so ¯\_(ツ)_/¯.