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fuzzgen: Add SIMD instructions supported by the interpreter (bytecode…
…alliance#5971) * fuzzgen: Add some SIMD instructions * fuzzgen: Remove `scalar_to_vector` Broken in the interpreter bytecodealliance#5911 * fuzzgen: Remove SIMD bitcasts Broken in the interpreter bytecodealliance#5915 * fuzzgen: Fix insert lane * fuzzgen: Remove debug code * fuzzgen: Remove vall_true This is broken in the interpreter bytecodealliance#5916 * fuzzgen: Disable a few more ops * fuzzgen: Remove `iadd_pairwise.i64x2` Turns out it doesen't exist * fuzzgen: Remove scalar `sqmul_round_sat` bytecodealliance#5923 * fuzzgen: Disable aligned loads to SIMD values * fuzzgen: Address Review Feedback Co-Authored-By: Jamey Sharp <jsharp@fastly.com> * fuzzgen: Rework `cmp` exclusion rules Co-Authored-By: Jamey Sharp <jsharp@fastly.com> --------- Co-authored-by: Jamey Sharp <jsharp@fastly.com>
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