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Add Ethernet and PLIC #19

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b6fd573
Add ethernet-controller
Yuan-Mao Feb 18, 2022
f2d8423
Add rv_plic
Yuan-Mao Feb 18, 2022
2df5051
Move IDELAYE2 out to ethernet_controller_wrapper
Yuan-Mao Apr 20, 2022
f6c8a9d
Update waveform
Yuan-Mao Apr 20, 2022
ea6193a
Rename
Yuan-Mao Apr 20, 2022
814b776
Increase reset cycle count
Yuan-Mao Apr 20, 2022
c069244
Remove mac_with_buffer
Yuan-Mao Apr 20, 2022
e97e117
Use bsg_edge_detect instead
Yuan-Mao Apr 20, 2022
8a4c299
Fix interrupt pending bug
Yuan-Mao Apr 20, 2022
cbc1e16
Add valid & ready signals for ethernet_controller
Yuan-Mao May 15, 2022
4d22fd0
Add a stage between ready_and_i and ready_and_o in ethernet_controlle…
Yuan-Mao Aug 9, 2022
fc0e60f
Update test
Yuan-Mao Aug 9, 2022
a052316
Remove ready_and_i/o signals
Yuan-Mao Aug 12, 2022
968ec4b
Update testbench
Yuan-Mao Aug 21, 2022
3a7fdb7
rgmii_phy_if, axis_async_fifo code refactoring
Yuan-Mao Aug 29, 2022
b74ad9d
Move last read latching logic out of bsg_mem_1rw
Yuan-Mao Aug 29, 2022
cbb7eda
Move RAM from axis_async_fifo into separate module
Yuan-Mao Aug 30, 2022
9c58474
Minor fix
Yuan-Mao Aug 30, 2022
4b8f07f
Code refactoring for eth_mac_1g_rgmii
Yuan-Mao Aug 30, 2022
c76dba5
Code refactoring for eth_mac_1g_rgmii_fifo
Yuan-Mao Aug 30, 2022
2c69aa0
Update reset
Yuan-Mao Aug 30, 2022
6516a37
Temp
Yuan-Mao Sep 2, 2022
6c819d0
Add custom axis_async_fifo
Yuan-Mao Sep 4, 2022
c450b24
Replace mem in axis_fifo
Yuan-Mao Sep 4, 2022
e1aa957
Change reset duration
Yuan-Mao Sep 5, 2022
46a17d5
Update arst_sync
Yuan-Mao Sep 5, 2022
7dc4cf1
Temp work
Yuan-Mao Sep 10, 2022
38b8ae0
Add bsg_store_and_forward
Yuan-Mao Sep 15, 2022
0f18f2b
Use bsg_fifo_1r1w_rolly in axis_async_fifo
Yuan-Mao Sep 15, 2022
90869b2
Add axis_async_fifo with 1 axis_fifo and 1 bsg_async_fifo
Yuan-Mao Oct 25, 2022
c2098d5
Move all clocks and resets out the top module && Fix testbench
Yuan-Mao Oct 30, 2022
274e6db
Minor fix
Yuan-Mao Nov 8, 2022
a9f3958
1. Remove all timescale
Yuan-Mao Nov 16, 2022
4ea79ce
1. Rearrange arst_sync
Yuan-Mao Nov 21, 2022
96807a5
1. Remove unused modules
Yuan-Mao Nov 21, 2022
4789eda
1. Rearrange directory structure -- remove template
Yuan-Mao Nov 21, 2022
439f509
Fix
Yuan-Mao Nov 21, 2022
099635f
Update new.tcl
Yuan-Mao Nov 24, 2022
6befc24
Update gitignore
Yuan-Mao Nov 27, 2022
0b49de4
Update
Yuan-Mao Nov 29, 2022
6867b34
Update zedboard.tcl
Yuan-Mao Nov 29, 2022
5b1c02f
Fix
Yuan-Mao Nov 30, 2022
5803c16
Fix width mismatches
Yuan-Mao Dec 14, 2022
22e045e
Fix reset duration
Yuan-Mao Dec 19, 2022
f05f16f
Fix naming
Yuan-Mao Feb 4, 2023
18592e0
Add tx_clk reset
Yuan-Mao Feb 4, 2023
9f23a39
Add gf14.tcl
Yuan-Mao Feb 4, 2023
a90eb3f
Add missing ethernet_controller_wrapper port
Yuan-Mao Feb 11, 2023
d5a91db
Remove default max delay; some fixes
Yuan-Mao Feb 12, 2023
7ff4238
Add opentitan
Yuan-Mao Feb 18, 2023
647d2ac
Update rv_plic directory structure
Yuan-Mao Feb 18, 2023
68d5b00
Remove basejump stl
Yuan-Mao Feb 18, 2023
9bdc505
Update ethernet_controller directory structure
Yuan-Mao Feb 18, 2023
a72410e
Pull out reset for iodelay ctrl
Yuan-Mao Feb 18, 2023
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9 changes: 9 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
**/DVEfiles/
**/csrc/
**/dump.*
**/flist.vcs
**/simv*
**/ucli.key
**/vc_hdrs.h
**/*.swp
**/*.swo
3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
[submodule "ethernet_controller/import/basejump_stl"]
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path = ethernet_controller/import/basejump_stl
url = https://github.com/bespoke-silicon-group/basejump_stl.git
Empty file added ethernet_controller/.gitignore
Empty file.
1 change: 1 addition & 0 deletions ethernet_controller/import/basejump_stl
Submodule basejump_stl added at 7f994b
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