Merge pull request #40 from apollo-lhc/release-v2.1

Release v2.1

.gitignore

@@ -1,6 +1,7 @@
 #tempfiles
 *~
 make_log.txt
+*.tar.gz
 
 #################################################################################
 ## Vivado files
@@ -15,6 +16,16 @@ cores/*/*
 #anything sub directories in the bd directory
 bd/*/*
 
+#picoblaze files
+*.fmt
+src/C2C_INTF/picoblaze/picoblaze/KCPSM6_session_log.txt
+src/C2C_INTF/picoblaze/picoblaze/Reprogram.script
+src/C2C_INTF/picoblaze/picoblaze/Update.script
+src/C2C_INTF/picoblaze/picoblaze/cli.log
+
+#ignore autogen cores
+configs/*/autogen/cores/
+
 #################################################################################
 ## config dirs
 #################################################################################

.gitmodules

@@ -6,3 +6,10 @@
 [submodule "regmap_helper"]
 	path = regmap_helper
 	url = https://github.com/BU-Tools/uHAL_AXI_regmap.git
+[submodule "src/misc"]
+	path = src/misc
+	url = https://gitlab.com/BU-EDF/fw-bits/misc-vhdl.git
+[submodule "build-scripts"]
+	path = build-scripts
+	url = https://gitlab.com/BU-EDF/fw-bits/build-scripts.git
+	branch = develop

Makefile

@@ -1,4 +1,4 @@
-include mk/helpers.mk
+-include build-scripts/mk/helpers.mk
 
 #################################################################################
 # VIVADO stuff
@@ -12,29 +12,36 @@ BUILD_VIVADO_SHELL=${BUILD_VIVADO_BASE}"/"$(BUILD_VIVADO_VERSION)"/settings64.sh
 #################################################################################
 # TCL scripts
 #################################################################################
-SETUP_TCL=${MAKE_PATH}/scripts/Setup.tcl
-BUILD_TCL=${MAKE_PATH}/scripts/Build.tcl
-SETUP_BUILD_TCL=${MAKE_PATH}/scripts/SetupAndBuild.tcl
-HW_TCL=${MAKE_PATH}/scripts/Run_hw.tcl
+BUILD_SCRIPTS_PATH=${MAKE_PATH}/build-scripts
+SETUP_TCL=${BUILD_SCRIPTS_PATH}/Setup.tcl
+BUILD_TCL=${BUILD_SCRIPTS_PATH}/Build.tcl
+SETUP_BUILD_TCL=${BUILD_SCRIPTS_PATH}/SetupAndBuild.tcl
+HW_TCL=${BUILD_SCRIPTS_PATH}/Run_hw.tcl
 
 #################################################################################
 # Source files
 #################################################################################
 PL_PATH=${MAKE_PATH}/src
 BD_PATH=${MAKE_PATH}/bd
 CORES_PATH=${MAKE_PATH}/cores
-ADDRESS_TABLE = ${MAKE_PATH}/os/address_table/address_CM.xml
-
+#ADDRESS_TABLE = ${MAKE_PATH}/os/address_table/address_apollo.xml
+$(BIT_BASE)%.bit $(BIT_BASE)%.svf	: ADDRESS_TABLE=${MAKE_PATH}/os/address_table_%/address_%.xml
 ################################################################################
 # Configs
 #################################################################################
+CONFIGS_BASE_PATH=configs/
 #get a list of the subdirs in configs.  These are our FPGA builds
-CONFIGS=$(patsubst configs/%/,%,$(dir $(wildcard configs/*/)))
+CONFIGS=$(patsubst ${CONFIGS_BASE_PATH}%/,%,$(dir $(wildcard ${CONFIGS_BASE_PATH}*/)))
 
 define CONFIGS_template =
- $(1): clean
+ $(1): clean autogen_clean_$(1)
 	time $(MAKE) $(BIT_BASE)$$(@).bit || $(MAKE) NOTIFY_DAN_BAD
 endef
+define CONFIGS_autoclean_template =
+ autogen_clean_$(1): 
+	@rm -rf ${CONFIGS_BASE_PATH}$(1)/autogen/*
+endef
+
 ################################################################################
 # Short build names
 #################################################################################
@@ -43,26 +50,26 @@ BIT_BASE=${MAKE_PATH}/bit/top_
 #################################################################################
 # preBuild 
 #################################################################################
-SLAVE_DEF_FILE_BASE=${MAKE_PATH}/configs/
+SLAVE_DEF_FILE_BASE=${MAKE_PATH}/${CONFIGS_BASE_PATH}
+ADDSLAVE_TCL_PATH=${MAKE_PATH}/src/ZynqPS/
 ADDRESS_TABLE_CREATION_PATH=${MAKE_PATH}/os/
 SLAVE_DTSI_PATH=${MAKE_PATH}/kernel/
+MAP_TEMPLATE_FILE=${MAKE_PATH}/regmap_helper/templates/axi_generic/template_map.vhd
 
-ifneq ("$(wildcard ${MAKE_PATH}/mk/preBuild.mk)","")
-  include ${MAKE_PATH}/mk/preBuild.mk
-endif
+-include ${BUILD_SCRIPTS_PATH}/mk/preBuild.mk
 
 
 
 #################################################################################
 # CM Address tables
 #################################################################################
-include mk/addrTable.mk
+-include build-scripts/mk/addrTable.mk
 
 #################################################################################
 # Device tree overlays
 #################################################################################
 DTSI_PATH=${SLAVE_DTSI_PATH}/hw/
-include mk/deviceTreeOverlays.mk
+-include build-scripts/mk/deviceTreeOverlays.mk
 
 
 .SECONDARY:
@@ -92,10 +99,14 @@ clean: clean_bd clean_ip clean_bit clean_kernel clean_prebuild
 clean_ip_%:
 	source $(BUILD_VIVADO_SHELL) &&\
 	cd ${MAKE_PATH}/proj &&\
-	vivado $(VIVADO_FLAGS) -source ${MAKE_PATH}/scripts/CleanIPs.tcl -tclargs ${MAKE_PATH} $(subst .bit,,$(subst clean_ip_,,$@))
+	vivado $(VIVADO_FLAGS) -source ${BUILD_SCRIPTS_PATH}/CleanIPs.tcl -tclargs ${MAKE_PATH} $(subst .bit,,$(subst clean_ip_,,$@))
+clean_autogen:
+	rm -rf ${CONFIGS_BASE_PATH}*/autogen/*
 
 clean_everything: clean clean_prebuild
 
+#generate autogen cleanup for this config
+$(foreach config,$(CONFIGS),$(eval $(call CONFIGS_autoclean_template,$(config))))
 
 #################################################################################
 # Open vivado
@@ -104,7 +115,7 @@ clean_everything: clean clean_prebuild
 open_project : 
 	source $(BUILD_VIVADO_SHELL) &&\
 	cd ${MAKE_PATH}/proj &&\
-	vivado top.xpr
+	vivado top.xpr -source ../build-scripts/OpenProject.tcl
 open_synth :
 	source $(BUILD_VIVADO_SHELL) &&\
 	cd ${MAKE_PATH}/proj &&\
@@ -131,30 +142,36 @@ interactive :
 	cd proj &&\
 	vivado -mode tcl
 
-$(BIT_BASE)%.bit $(BIT_BASE)%.svf	: $(SLAVE_DTSI_PATH)/slaves_%.yaml $(ADDRESS_TABLE_CREATION_PATH)/slaves_%.yaml
+
+$(BIT_BASE)%.bit $(BIT_BASE)%.svf	: $(SLAVE_DTSI_PATH)/config_%.yaml $(ADDRESS_TABLE)
 	source $(BUILD_VIVADO_SHELL) &&\
 	mkdir -p ${MAKE_PATH}/kernel/hw &&\
 	mkdir -p ${MAKE_PATH}/proj &&\
 	mkdir -p ${MAKE_PATH}/bit &&\
 	cd proj &&\
-	vivado $(VIVADO_FLAGS) -source $(SETUP_BUILD_TCL) -tclargs ${MAKE_PATH} $(subst .bit,,$(subst ${BIT_BASE},,$@)) $(OUTPUT_MARKUP)
-	$(MAKE) NOTIFY_DAN_GOOD
-	$(MAKE) overlays
-	$(MAKE) ${MAKE_PATH}/os/address_table/address_$*.xml
-	@echo 	$(MAKE) $*.tar.gz
-	$(MAKE) $*.tar.gz
+	vivado $(VIVADO_FLAGS) -source $(SETUP_BUILD_TCL) -tclargs ${MAKE_PATH} ${BUILD_SCRIPTS_PATH} $(subst .bit,,$(subst ${BIT_BASE},,$@)) $(OUTPUT_MARKUP)
+	$(MAKE) NOTIFY_DAN_GOOD  $(OUTPUT_MARKUP)
+	$(MAKE) overlays  $(OUTPUT_MARKUP)
+	@rm -f $*.tar.gz
+	$(MAKE) $*.tar.gz  $(OUTPUT_MARKUP)
 
 SVF	:
 	@$(VIVADO_SETUP) &&\
-	vivado $(VIVADO_FLAGS) -source ${MAKE_PATH}/scripts/Generate_svf.tcl $(OUTPUT_MARKUP)
+	vivado $(VIVADO_FLAGS) -source ${BUILD_SCRIPTS_PATH}/Generate_svf.tcl $(OUTPUT_MARKUP)
 
 
+#convert all push urls to ssh
 init:
 	git submodule update --init --recursive
+	@git submodule foreach 'git remote -v | grep http |  grep \(push\) | sed -e "i\git remote set-url --push " -e "s/http.*\/\//git\@/" -e "s/\//:/" -e"s/(push)//" | xargs | bash'
+
+
+
 
 
 make test :
 	@echo $(CONFIGS)
 
-%.tar.gz : bit/top_%.svf kernel/hw/dtbo/*.dtbo os/address_table/
-	@tar -zcf $@ $< -C kernel/hw/ dtbo -C ../../os/ address_table
+#%.tar.gz : bit/top_%.svf kernel/hw/dtbo/ os/address_table/
+%.tar.gz : bit/top_%.svf 
+	@tar -h -zcf $@ $< -C kernel/hw/ dtbo -C ../../os/ address_table

README.md

@@ -21,19 +21,22 @@ In these folders you will need to have atleast the following three files:
    - xci_files  : the list of IP core xci files used
  - settings.tcl  
    This file primarily lists the FPGA part number
- - slaves.yaml 
+ - config.yaml 
    Lists AXI slaves that exist or should be made, their AXI address info, uHAL address/tables, and if they should auto generate AXI slave decoding logic from the uHAL address tables
+   This can also list certain IP cores that will be generated and the parameters used for them (Currently clocking, some MGT, and ILA cores.)
 
 #### Additional files
 
      This is where files that can't be generic should be put, but that is not a requirement. 
-     I would suggest that all non-shared cores be saved as: configs/CM_FPGA/cores/name/name.xci
-     I would also suggest that non-shared HDL be put in configs/CM_FPGA/src, but you are free to do what you like. 
+     I would suggest that all non-shared cores be saved as: configs/CM_FPGA_NAME/cores/name/name.xci
+     I would also suggest that non-shared HDL be put in configs/CM_FPGA_NAME/src, but you are free to do what you like. 
+     Common files used in multiple builds are normally put in src/your_dir_name, but this isn't strictly enforced, so be reasonable. 
      These files used are always taken from the files.tcl (with the exception of the autogenerated FW info hdl file)
 
 
 ### Building
 As mentioned above, make is used to drive the build.
+ - If you just checked this out, do a "make init" to pull all the included submodules. 
  - FPGA FW build 
    Located in the main directory (with this file)
    Builds the CM FPGA FW   
@@ -56,20 +59,21 @@ Buildable Groups:
 
 #### FW
 To Build FPGA FW:
-  `make group_revN_FPGA`, e.g., for Cornell CM Rev1 with 7 series zynq, VU7P FPGA: `make Cornell_rev1_p2_VU7p-1-SM_7s`
+  `make group_revN_FPGA`, e.g., for Cornell CM Rev1 with 7 series SM zynq, VU7P FPGA: `make Cornell_rev1_p2_VU7p-1-SM_7s`
 
 
   Ouput:
+   - ./group_revN_FPGA.tar.gz which includes
+
+     - bit/top_group_revN_FPGA.bit
 
-   - bit/top_group_revN_FPGA.bit
-
-   - kernel/hw/*.dtsi_chunk,*.dtsi_post_chunk,hwdef
+     - kernel/hw/*.dtsi_chunk,*.dtsi_post_chunk,hwdef
 
 ### Organization:
-  Build scripts are in ./scripts and are called by the Makefile
+  Build scripts are in ./build-scripts and are called by the Makefile
 
   HDL & constraint files are in ./configs/group_revN_FPGA/src.
-  slaves.yaml in ./config lists the slaves to be built and the tcl needed to build them
+  config.yaml in ./config lists the slaves to be built and the tcl needed to build them
   Output HDL _map.vhd and _PKG.vhd, and AddSlaves.tcl are autogenerated, but commited to git so UHAL isn't required to do simple builds 
 
 

address_table/modules/C2C_INTF.xml

@@ -0,0 +1,19 @@
+<node id="C2C_INTF">  
+  <!-- DRP 0x0 to 0x3FF -> 0x0 to 0x3FF-->
+  <node id="DRP"               address="0x000" fwinfo="type=mem16_0x400" module="file://DRP_USP_GTH.xml"/>
+  <!-- STATUS 0x0 to 0x0 -> 0x400 to 0x400 -->
+  <node id="STATUS"            address="0x400" module="file://CM_C2C_Status.xml"/>
+  <!-- DEBUG 0x0 to 0x5 -> 0x404 to 0x409 -->
+  <node id="DEBUG"             address="0x404" module="file://MGT_DEBUG_USP.xml"/>
+  <!-- COUNTERS 0x0 to 0xA  -> 0x410 to 0x41A -->
+  <node id="COUNTERS"          address="0x410" module="file://CM_C2C_CNT.xml"/>
+
+  <node id="USER_FREQ"         address="0x420" permission="r" mask="0xFFFFFFFF" description="Measured Freq of clock" parameters="Table=CLOCKING;Column=FREQ;Row=_1_2_3;Status=3;Show=nz;Format=m_1_1_1000000_1_0_1" />
+  <node id="ENABLE_PHY_CTRL"   address="0x421" mask="0x01000000"  permission="rw" description="phy_lane_control is enabled"                   parameters="Table=C2C;Column=_1_2;Row=_3;Status=1;show=nz;default=0x1"/>
+  <node id="PHY_READ_TIME"     address="0x421" mask="0x00FFFFFF"  permission="rw" description="Time spent waiting for phylane to stabilize"   parameters="default=0x4C4B40"/> <!-- 100ms default -->       
+  <node id="PHY_LANE_STABLE"   address="0x422" mask="0x000FFFFF"  permission="rw" description="Contious phy_lane_up signals required to lock phylane control" parameters="default=0xFF"/>
+  <node id="PHY_LANE_ERRORS_TO_RESET"   address="0x423" mask="0x000000FF"  permission="rw" description="Number of failures before we reset the pma" parameters="default=0xFF"/>
+  <node id="PHY_MAX_SINGLE_BIT_ERROR_RATE"   address="0x424" mask="0xFFFFFFFF"  permission="rw" description="Max single bit error rate" parameters="default=0xFFFF"/>
+  <node id="PHY_MAX_MULTI_BIT_ERROR_RATE"    address="0x425" mask="0xFFFFFFFF"  permission="rw" description="Max multi bit error rate" parameters="default=0xFFFF"/>
+
+</node>

address_table/modules/C2C_INTFS.xml

@@ -0,0 +1,11 @@
+<node id="C2C_INTFS">  
+  <node id="C2C_1"    address="0x0000" fwinfo="type=array" module="file://C2C_INTF.xml"/>
+  <node id="C2C_2"    address="0x1000" fwinfo="type=array" module="file://C2C_INTF.xml"/>
+  <node id="PB" address="0x2000">
+    <node id="MEM" mode="incremental" size="0x800" address="0x000" fwinfo="type=mem18_0x800" />
+    <node id="RESET" address="0x800" mask="0x00000001" permission="rw"/>  
+    <node id="IRQ_COUNT" address="0x801" mask="0xFFFFFFFF" permission="rw" parameters="default=10000000"/>                                                                 
+
+  </node>
+
+</node>

address_table/modules/CM_C2C_CNT.xml

@@ -0,0 +1,20 @@
+<node id="CNT">
+  <node id="ERRORS_ALL_TIME"          address="0x0" permission="r"  description="Counter for all errors while locked"      parameters="Table=C2C;Row=PHY_ERRORS;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="ERRORS_SINCE_LOCKED"      address="0x1" permission="r"  description="Counter for errors since locked"          parameters="Table=C2C;Row=PHY_ERRORS_CURRENT;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="CONFIG_ERROR_COUNT"       address="0x2" permission="r"  description="Counter for CONFIG_ERROR"                 parameters="Table=C2C;Row=CONFIG_ERROR_COUNT;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="LINK_ERROR_COUNT"         address="0x3" permission="r"  description="Counter for LINK_ERROR"                   parameters="Table=C2C;Row=LINK_ERROR_COUNT;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="MB_ERROR_COUNT"           address="0x4" permission="r"  description="Counter for MB_ERROR"                     parameters="Table=C2C;Row=MB_ERROR_COUNT;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="PHY_HARD_ERROR_COUNT"     address="0x5" permission="r"  description="Counter for PHY_HARD_ERROR"               parameters="Table=C2C;Row=PHY_HARD_ERR_COUNT;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="PHY_SOFT_ERROR_COUNT"     address="0x6" permission="r"  description="Counter for PHY_SOFT_ERROR"               parameters="Table=C2C;Row=PHY_SOFT_ERR_COUNT;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="PHYLANE_STATE"            address="0x7" permission="r"  description="Current state of phy_lane_control module" parameters="Table=C2C;Row=PHYLANE_STATE;Column=_1_2;Status=1;Format=t_0_INIT_1_resetWAIT_2_initWAIT_4_RUNNING" mask="0x7"/>
+  <node id="RESET_COUNTERS"           address="0x8" permission="w" description="Reset counters in Monitor" mask="0x1"/>
+  <node id="ERROR_WAITS_SINCE_LOCKED" address="0x9" permission="r"  description="Count for phylane in error state"         parameters="Table=C2C;Row=PHY_ERROR_WINDOWS;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="USER_CLK_FREQ"            address="0xA" permission="r"  description="Frequency of the user C2C clk"            parameters="Table=C2C;Row=C2C_FREQ;Column=_1_2;Status=2;Show=nz;Format=m_1_1_1000000_1_0_1"/>
+  <node id="XCVR_RESETS"              address="0xB" permission="r"  description="Count for phylane in error state"         parameters="Table=C2C;Row=PHY_RESETS;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="WAITING_TIMEOUTS"         address="0xC" permission="r"  description="Count of initialize cycles"         parameters="Table=C2C;Row=PHY_RESETS;Column=_1_2;Status=1;Show=nz;Format=u"/>
+  <node id="SB_ERROR_RATE"            address="0xD" permission="r"  description="single bit error rate"         parameters="Table=C2C;Column=_1_2;Row=SB_ERROR_RATE;Statu\
+s=1;Show=nz;Format=u"/>                                                                                                                                                   
+  <node id="MB_ERROR_RATE"            address="0xE" permission="r"  description="multi bit error rate"         parameters="Table=C2C;Column=_1_2;Row=MB_ERROR_RATE;Status\
+=1;Show=nz;Format=u"/>     
+</node>
+