Merge pull request #32 from apollo-lhc/release-v2.0

Release v2.0
apollo-lhc · Aug 12, 2021 · 50b8bb9 · 50b8bb9
2 parents e2191c6 + 7114b93
commit 50b8bb9
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diff --git a/.gitignore b/.gitignore
@@ -15,6 +15,12 @@ cores/*/*
 #anything sub directories in the bd directory
 bd/*/*
 
+#################################################################################
+## config dirs
+#################################################################################
+configs/*/cores/*/*
+!configs/*/cores/*/*.xci
+
 #################################################################################
 ## Output files
 #################################################################################

diff --git a/Makefile b/Makefile
@@ -1,125 +1,160 @@
-#################################################################################
-# make stuff
-#################################################################################
-#output markup
-OUTPUT_MARKUP= 2>&1 | tee ../make_log.txt | ccze -A
+include mk/helpers.mk
 
 #################################################################################
 # VIVADO stuff
 #################################################################################
-VIVADO_VERSION=2018.2
 VIVADO_FLAGS=-notrace -mode batch
-VIVADO_SHELL="/opt/Xilinx/Vivado/"$(VIVADO_VERSION)"/settings64.sh"
-VIVADO_SETUP=source $(VIVADO_SHELL) && mkdir -p proj && mkdir -p kernel/hw && cd proj
+BUILD_VIVADO_VERSION?=2020.2
+BUILD_VIVADO_BASE?="/work/Xilinx/Vivado"
+BUILD_VIVADO_SHELL=${BUILD_VIVADO_BASE}"/"$(BUILD_VIVADO_VERSION)"/settings64.sh"
 
 
 #################################################################################
 # TCL scripts
 #################################################################################
-SETUP_TCL=scripts/Setup.tcl
-BUILD_TCL=scripts/Build.tcl
-SETUP_BUILD_TCL=scripts/SetupAndBuild.tcl
-HW_TCL=scripts/Run_hw.tcl
+SETUP_TCL=${MAKE_PATH}/scripts/Setup.tcl
+BUILD_TCL=${MAKE_PATH}/scripts/Build.tcl
+SETUP_BUILD_TCL=${MAKE_PATH}/scripts/SetupAndBuild.tcl
+HW_TCL=${MAKE_PATH}/scripts/Run_hw.tcl
 
 #################################################################################
 # Source files
 #################################################################################
-PL_PATH=../src
-BD_PATH=../bd
-CORES_PATH=../cores
+PL_PATH=${MAKE_PATH}/src
+BD_PATH=${MAKE_PATH}/bd
+CORES_PATH=${MAKE_PATH}/cores
+ADDRESS_TABLE = ${MAKE_PATH}/os/address_table/address_CM.xml
 
-SYM_LNK_XMLS = $(shell find ./ -type l)
-MAP_OBJS = $(patsubst %.xml, %_map.vhd, $(SYM_LNK_XMLS))
-PKG_OBJS = $(patsubst %.xml, %_PKG.vhd, $(SYM_LNK_XMLS))
+################################################################################
+# Configs
+#################################################################################
+#get a list of the subdirs in configs.  These are our FPGA builds
+CONFIGS=$(patsubst configs/%/,%,$(dir $(wildcard configs/*/)))
 
+define CONFIGS_template =
+ $(1): clean
+	time $(MAKE) $(BIT_BASE)$$(@).bit || $(MAKE) NOTIFY_DAN_BAD
+endef
 ################################################################################
 # Short build names
 #################################################################################
+BIT_BASE=${MAKE_PATH}/bit/top_
 
-BIT=./bit/top.bit
+#################################################################################
+# preBuild 
+#################################################################################
+SLAVE_DEF_FILE_BASE=${MAKE_PATH}/configs/
+ADDRESS_TABLE_CREATION_PATH=${MAKE_PATH}/os/
+SLAVE_DTSI_PATH=${MAKE_PATH}/kernel/
 
-.SECONDARY:
+ifneq ("$(wildcard ${MAKE_PATH}/mk/preBuild.mk)","")
+  include ${MAKE_PATH}/mk/preBuild.mk
+endif
 
-.PHONY: clean list bit
 
-all: bit 
 
 #################################################################################
-# preBuild 
+# CM Address tables
 #################################################################################
-SLAVE_DEF_FILE=src/slaves.yaml
-ADDSLAVE_TCL_PATH=src/c2cSlave/
-ADDRESS_TABLE_CREATION_PATH=os/
-SLAVE_DTSI_PATH=kernel/
+include mk/addrTable.mk
 
-ifneq ("$(wildcard mk/preBuild.mk)","")
-  include mk/preBuild.mk
-endif
+#################################################################################
+# Device tree overlays
+#################################################################################
+DTSI_PATH=${SLAVE_DTSI_PATH}/hw/
+include mk/deviceTreeOverlays.mk
+
+
+.SECONDARY:
 
+.PHONY: clean list bit NOTIFY_DAN_BAD NOTIFY_DAN_GOOD init $(CONFIGS) $(PREBUILDS)
 
 #################################################################################
 # Clean
 #################################################################################
 clean_ip:
 	@echo "Cleaning up ip dcps"
-	@find ./cores -type f -name '*.dcp' -delete
+	@find ${MAKE_PATH}/cores -type f -name '*.dcp' -delete
 clean_bd:
 	@echo "Cleaning up bd generated files"
-	@rm -rf ./bd/zynq_bd
-	@rm -rf ./bd/c2cSlave
+	@rm -rf ${MAKE_PATH}/bd/zynq_bd
+	@rm -rf ${MAKE_PATH}/bd/c2cSlave
 clean_bit:
 	@echo "Cleaning up bit files"
-	@rm -rf ./bit/*
-clean_os:
-	@echo "Clean OS hw files"
-	@rm -f kernel/hw/*
-clean: clean_bd clean_ip clean_bit clean_os
-	@rm -rf ./proj/*
+	@rm -rf ${MAKE_PATH}/bit/*
+clean_kernel:
+	@echo "Clean hw files"
+	@rm -rf ${MAKE_PATH}/kernel/hw/*
+clean: clean_bd clean_ip clean_bit clean_kernel clean_prebuild 
+	@rm -rf ${MAKE_PATH}/proj/*
+	@rm -f make_log.txt
 	@echo "Cleaning up"
+clean_ip_%:
+	source $(BUILD_VIVADO_SHELL) &&\
+	cd ${MAKE_PATH}/proj &&\
+	vivado $(VIVADO_FLAGS) -source ${MAKE_PATH}/scripts/CleanIPs.tcl -tclargs ${MAKE_PATH} $(subst .bit,,$(subst clean_ip_,,$@))
+
+clean_everything: clean clean_prebuild
 
 
 #################################################################################
 # Open vivado
 #################################################################################
 
 open_project : 
-	@$(VIVADO_SETUP) &&\
+	source $(BUILD_VIVADO_SHELL) &&\
+	cd ${MAKE_PATH}/proj &&\
 	vivado top.xpr
 open_synth :
-	@$(VIVADO_SETUP) &&\
+	source $(BUILD_VIVADO_SHELL) &&\
+	cd ${MAKE_PATH}/proj &&\
 	vivado post_synth.dcp
 open_impl :
-	@$(VIVADO_SETUP) &&\
+	source $(BUILD_VIVADO_SHELL) &&\
+	cd ${MAKE_PATH}/proj &&\
 	vivado post_route.dcp
 open_hw :
-	@$(VIVADO_SETUP) &&\
-	vivado -source ../$(HW_TCL)
+	source $(BUILD_VIVADO_SHELL) &&\
+	cd ${MAKE_PATH}/proj &&\
+	vivado -source $(HW_TCL)
 
 
 #################################################################################
 # FPGA building
 #################################################################################
-bit	: $(BIT)
+#generate a build rule for each FPGA in the configs dir ($CONFIGS)c
+$(foreach config,$(CONFIGS),$(eval $(call CONFIGS_template,$(config))))
 
 interactive : 
-	@$(VIVADO_SETUP) &&\
+	source $(BUILD_VIVADO_SHELL) &&\
+	mkdir -p ${MAKE_PATH}/proj &&\
+	cd proj &&\
 	vivado -mode tcl
-$(BIT)	:
-	@mkdir -p bit
-	@$(VIVADO_SETUP) &&\
-	vivado $(VIVADO_FLAGS) -source ../$(SETUP_BUILD_TCL) $(OUTPUT_MARKUP)
-SVF	:
-	@$(VIVADO_SETUP) &&\
-	vivado $(VIVADO_FLAGS) -source ../scripts/Generate_svf.tcl $(OUTPUT_MARKUP)
 
+$(BIT_BASE)%.bit $(BIT_BASE)%.svf	: $(SLAVE_DTSI_PATH)/slaves_%.yaml $(ADDRESS_TABLE_CREATION_PATH)/slaves_%.yaml
+	source $(BUILD_VIVADO_SHELL) &&\
+	mkdir -p ${MAKE_PATH}/kernel/hw &&\
+	mkdir -p ${MAKE_PATH}/proj &&\
+	mkdir -p ${MAKE_PATH}/bit &&\
+	cd proj &&\
+	vivado $(VIVADO_FLAGS) -source $(SETUP_BUILD_TCL) -tclargs ${MAKE_PATH} $(subst .bit,,$(subst ${BIT_BASE},,$@)) $(OUTPUT_MARKUP)
+	$(MAKE) NOTIFY_DAN_GOOD
+	$(MAKE) overlays
+	$(MAKE) ${MAKE_PATH}/os/address_table/address_$*.xml
+	@echo 	$(MAKE) $*.tar.gz
+	$(MAKE) $*.tar.gz
 
-#################################################################################
-# Help 
-#################################################################################
+SVF	:
+	@$(VIVADO_SETUP) &&\
+	vivado $(VIVADO_FLAGS) -source ${MAKE_PATH}/scripts/Generate_svf.tcl $(OUTPUT_MARKUP)
 
-#list magic: https://stackoverflow.com/questions/4219255/how-do-you-get-the-list-of-targets-in-a-makefile
-list:
-	@$(MAKE) -pRrq -f $(MAKEFILE_LIST) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$' | column
 
 init:
 	git submodule update --init --recursive
+
+
+make test :
+	@echo $(CONFIGS)
+
+%.tar.gz : bit/top_%.svf kernel/hw/dtbo/*.dtbo os/address_table/
+	@tar -zcf $@ $< -C kernel/hw/ dtbo -C ../../os/ address_table
diff --git a/README.md b/README.md
@@ -1,11 +1,86 @@
-# CM_Kintex_FW
-APOLLO Command Module Kintex FPGA FW
+# APOLLO Command Module firmware
 
-Requirements:
-Vivado 2018.2 installed in /opt/Xilinx/Vivado/2018.2/
-make
+## Github branching policy:
+We are going to try to follow: https://nvie.com/posts/a-successful-git-branching-model/
+The default branch is develop and you should branch off of that.
 
-Build instructions:
->make clean;make
+## Building
+There are several Apollo CMs so this build system is setup to make any of them.
+The differences between these configurations are located in the "configs" directory.
+The build process uses Vivado but is directed by makefiles. 
 
+### configs
+The configs directory contains directories for each different configuraiton and the name of this directory should match the make rule.
+In these folders you will need to have atleast the following three files:
+ - files.tcl  
+   A tcl file that lists the files to be included
+   There are
+   - bd_files   : the list of BD names and tcl files to be built
+   - vhdl_files : the list of VHDL files this project uses
+   - xdc_files  : the list of xdc files for the project
+   - xci_files  : the list of IP core xci files used
+ - settings.tcl  
+   This file primarily lists the FPGA part number
+ - slaves.yaml 
+   Lists AXI slaves that exist or should be made, their AXI address info, uHAL address/tables, and if they should auto generate AXI slave decoding logic from the uHAL address tables
 
+#### Additional files
+
+     This is where files that can't be generic should be put, but that is not a requirement. 
+     I would suggest that all non-shared cores be saved as: configs/CM_FPGA/cores/name/name.xci
+     I would also suggest that non-shared HDL be put in configs/CM_FPGA/src, but you are free to do what you like. 
+     These files used are always taken from the files.tcl (with the exception of the autogenerated FW info hdl file)
+
+
+### Building
+As mentioned above, make is used to drive the build.
+ - FPGA FW build 
+   Located in the main directory (with this file)
+   Builds the CM FPGA FW   
+
+
+#### Make
+Buildable Groups:
+  > make list
+
+    - Apollo CM config:
+      Different FWs to make (you probably just want one of these)
+    - Vivado:
+      Drive interactive vivado sessions
+    - Clean:
+      Clean different parts of the builds
+    - Tests:
+      Test benches run and compared against golden outputs
+    - Test-benches:
+      Start interactive test-benches
+
+#### FW
+To Build FPGA FW:
+  `make group_revN_FPGA`, e.g., for Cornell CM Rev1 with 7 series zynq, VU7P FPGA: `make Cornell_rev1_p2_VU7p-1-SM_7s`
+
+
+  Ouput:
+
+   - bit/top_group_revN_FPGA.bit
+
+   - kernel/hw/*.dtsi_chunk,*.dtsi_post_chunk,hwdef
+
+### Organization:
+  Build scripts are in ./scripts and are called by the Makefile
+
+  HDL & constraint files are in ./configs/group_revN_FPGA/src.
+  slaves.yaml in ./config lists the slaves to be built and the tcl needed to build them
+  Output HDL _map.vhd and _PKG.vhd, and AddSlaves.tcl are autogenerated, but commited to git so UHAL isn't required to do simple builds 
+
+
+### Dependencies:
+  - Vivado 2018.2 installed in ${BUILD_VIVADO_BASE}
+  - python2
+  - python-yaml
+  - python-jinja2
+  - uHAL (set CACTUS_ROOT and LD_LIBARARY_PATH accordingly)
+  - device tree compiler (rpm name "dtc")
+  - make
+
+### Environment variables
+To override the version and/or location of the Xilinx tools, set the BUILD_VIVADO_VERSION and BUILD_VIVADO_BASE variables. A custom CACTUS location can be set by setting CACTUS_ROOT (you might also need to set PYTHON_ROOT).
diff --git a/address_table/modules/CM_C2C_DEBUG_USP.xml b/address_table/modules/CM_C2C_DEBUG_USP.xml
@@ -0,0 +1,43 @@
+<node id="LINK_DEBUG">
+  <node id="QPLL_LOCK"          address="0x0" mask="0x00010000" permission="r"  description="DEBUG cplllock" />
+  <node id="CPLL_LOCK"          address="0x0" mask="0x00100000" permission="r"  description="DEBUG cplllock" />
+  <node id="EYESCAN_DATA_ERROR" address="0x0" mask="0x00200000" permission="r"  description="DEBUG eyescan data error" />
+  <node id="EYESCAN_RESET"      address="0x0" mask="0x00400000" permission="rw" description="DEBUG eyescan reset" />
+  <node id="EYESCAN_TRIGGER"    address="0x0" mask="0x00800000" permission="rw" description="DEBUG eyescan trigger" />
+  <node id="DMONITOR"           address="0x0" mask="0x0000FFFF" permission="r"  description="DEBUG d monitor" />
+  <node id="PCS_RSV_DIN"        address="0x1" mask="0x0000FFFF" permission="rw" description="bit 2 is DRP uber reset" />
+
+  <node id="RX" address="0x2">
+    <node id="BUF_STATUS"                      mask="0x00000007" permission="r"  description="DEBUG rx buf status" />
+    <node id="PRBS_ERR"                        mask="0x00000400" permission="r"  description="DEBUG rx PRBS error" />
+    <node id="RESET_DONE"                      mask="0x00000800" permission="r"  description="DEBUG rx reset done" />
+    <node id="BUF_RESET"                       mask="0x00001000" permission="rw" description="DEBUG rx buf reset" />
+    <node id="CDR_HOLD"                        mask="0x00002000" permission="rw" description="DEBUG rx CDR hold" />
+    <node id="DFE_LPM_RESET"                   mask="0x00020000" permission="rw" description="DEBUG rx DFE LPM RESET" />
+    <node id="LPM_EN"                          mask="0x00040000" permission="rw" description="DEBUG rx LPM ENABLE" />
+    <node id="PCS_RESET"                       mask="0x00800000" permission="rw" description="DEBUG rx pcs reset" />
+    <node id="PMA_RESET"                       mask="0x01000000" permission="rw" description="DEBUG rx pma reset" />
+    <node id="PRBS_CNT_RST"                    mask="0x02000000" permission="rw" description="DEBUG rx PRBS counter reset" />
+    <node id="PRBS_SEL"                        mask="0x3C000000" permission="rw" description="DEBUG rx PRBS select" />
+    <node id="RATE"              address="0x1" mask="0x00000007" permission="rw" description="DEBUG rx rate" />
+
+  </node>
+
+  <node id="TX" address="0x4">
+    <node id="BUF_STATUS"                   mask="0x00000003" permission="r"  description="DEBUG tx buf status" />
+    <node id="RESET_DONE"                   mask="0x00000004" permission="r"  description="DEBUG tx reset done" />
+    <node id="INHIBIT"                      mask="0x00000080" permission="rw" description="DEBUG tx inhibit" />
+    <node id="PCS_RESET"                    mask="0x00008000" permission="rw" description="DEBUG tx pcs reset" />
+    <node id="PMA_RESET"                    mask="0x00010000" permission="rw" description="DEBUG tx pma reset" />
+    <node id="POLARITY"                     mask="0x00020000" permission="rw" description="DEBUG tx polarity" />
+    <node id="POST_CURSOR"                  mask="0x007C0000" permission="rw" description="DEBUG post cursor" />
+    <node id="PRBS_FORCE_ERR"               mask="0x00800000" permission="rw" description="DEBUG force PRBS error" />
+    <node id="PRE_CURSOR"                   mask="0xF8000000" permission="rw" description="DEBUG pre cursor" />
+    <node id="PRBS_SEL"       address="0x1" mask="0x0000000F" permission="rw" description="DEBUG PRBS select" />
+    <node id="DIFF_CTRL"      address="0x1" mask="0x000001F0" permission="rw" description="DEBUG tx diff control" />
+  </node>
+</node>
+
+
+
+
diff --git a/address_table/modules/CM_C2C_Status.xml b/address_table/modules/CM_C2C_Status.xml
@@ -0,0 +1,19 @@
+<node id="STATUS">
+  <node id="CONFIG_ERROR"       address="0x0" mask="0x00000001" permission="r"  description="C2C config error"         parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz"/>
+  <node id="LINK_ERROR"         address="0x0" mask="0x00000002" permission="r"  description="C2C link error"           parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz"/>
+  <node id="LINK_GOOD"          address="0x0" mask="0x00000004" permission="r"  description="C2C link FSM in SYNC"     parameters="Table=C2C;Column=_4;Row=_1_2;Status=1"/>
+  <node id="MB_ERROR"           address="0x0" mask="0x00000008" permission="r"  description="C2C multi-bit error"      parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz"/>
+  <node id="DO_CC"              address="0x0" mask="0x00000010" permission="r"  description="Aurora do CC"             parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=z"/>
+  <node id="INITIALIZE"         address="0x0" mask="0x00000020" permission="rw" description="C2C initialize"           parameters="Table=C2C;Column=_4;Row=_1_2;Status=2"/>
+  <node id="PHY_RESET"          address="0x0" mask="0x00000100" permission="r"  description="Aurora phy in reset"      parameters="Table=C2C;Column=_4;Row=_1_2;Status=2"/>
+  <node id="PHY_GT_PLL_LOCK"    address="0x0" mask="0x00000200" permission="r"  description="Aurora phy GT PLL locked" parameters="Table=C2C;Column=_4;Row=_1_2;Status=2"/>
+  <node id="PHY_MMCM_LOL"       address="0x0" mask="0x00000400" permission="r"  description="Aurora phy mmcm LOL"      parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz"/>
+  <node id="PHY_LANE_UP"        address="0x0" mask="0x00003000" permission="r"  description="Aurora phy lanes up"      parameters="Table=C2C;Column=_4;Row=_1_2;Status=1"/>
+  <node id="PHY_HARD_ERR"       address="0x0" mask="0x00010000" permission="r"  description="Aurora phy hard error"    parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz"/>
+  <node id="PHY_SOFT_ERR"       address="0x0" mask="0x00020000" permission="r"  description="Aurora phy soft error"    parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz"/>
+  <node id="CHANNEL_UP"         address="0x0" mask="0x00040000" permission="r"  description="Channel up"               parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz"/>
+  <node id="LINK_IN_FW"         address="0x0" mask="0x80000000" permission="r"  description="FW includes this link"    parameters="Table=C2C;Column=_4;Row=_1_2;Status=2;Show=nz;default=0x0"/>
+
+
+</node>
+