max3421e: Update some comments and a README. Cosmetic only.

PX4 · Jul 31, 2018 · d543937 · d543937
1 parent d252c79
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Showing 2 changed files with 18 additions and 11 deletions.
diff --git a/configs/viewtool-stm32f107/README.txt b/configs/viewtool-stm32f107/README.txt
@@ -706,34 +706,36 @@ MAX3421E Integration
 
   USBHostShield-v13 (See schematic).
 
-  DuinoFun UHS mini v2.0.  No schematics available.  This is the pinout:
+  DuinoFun UHS mini v2.0.  No schematics available.  This is how the pins
+  are labeled:
 
-     INT                                                  MAX_RST?
+     INT                                                 MAX_RST
       o     o     o     o     o     o     o     o     o     o     o     o
       o     o     o     o     o
-     V_BUS INT   GPX MAX_RST  SS
+    V_BUS  INT   GPX MAX_RST  SS
 
       o     o     o     o     o     o     o     o     o     o     o     o
-      SS   CLK*  MISO  MOSI*                         VCC         GND
+      SS   CLK*  MISO  MOSI*                         VCC         GND**
 
-  NOTE:  There is a error in the silkscreen:  The pin labeled CLK is actually
-  MOSI; the pin labeled MOST is the clock
+  *  NOTE:  There is a error in the silkscreen:  The pin labeled CLK is
+     actually MOSI; the pin labeled MOSI is the clock
+  ** Not labeled
 
   Using SPI1 on J8 pins 7-12, discretes on J18
 
     ------ ----------- ----------- ------------------ ----------------------
     NAME   VIEWTOOL    STM32       USBHostShield-v13  DuinoFun UHS mini v2.0
     ------ ----------- ----------- ------------------ ----------------------
     CS#    J8  Pin 12  PA4/NSS1    D10                SS
-    SCK    J8  Pin 11  PA5/SCK1    D13                MOSI (label wrong)
+    SCK    J8  Pin 11  PA5/SCK1    D13                CLK (label MOSI)
     MISO   J8  Pin  9  PA6/MISO1   D12                MISO
-    MOSI   J8  Pin 10  PA7/MOSI1   D11                CLK (label wrong)
+    MOSI   J8  Pin 10  PA7/MOSI1   D11                MOSI (label CLK)
     INT#   J18 Pin 10  PA0         D9                 INT
     RST#   J18 Pin  8  PA1         D7                 MAX_RST
     GPX                            D8                 GPX
     VBUS   J18 Pin  2  5V          VIN                V_BUS
     3.3V   J8  Pin  7              N/C                VCC
-    GND    J8  Pin  8              GND                GND
+    GND    J8  Pin  8              GND                GND (no label)
 
   Using SPI2 on J8 pins 1-6, discretes on J18
 

diff --git a/configs/viewtool-stm32f107/src/stm32_max3421e.c b/configs/viewtool-stm32f107/src/stm32_max3421e.c
@@ -190,15 +190,20 @@ static void max3421e_enable(FAR const struct max3421e_lowerhalf_s *lower,
     (FAR struct viewtool_max3421elower_s *)lower;
   irqstate_t flags;
 
+  uinfo("enable=%u handler=%p\n", enable, priv->handler);
+
   /* Attach and enable, or detach and disable.  Enabling and disabling GPIO
    * interrupts is a multi-step process so the safest thing is to keep
    * interrupts disabled during the reconfiguration.
    */
 
   flags = enter_critical_section();
-  if (enable && priv->handler)
+  if (enable && priv->handler != NULL)
     {
-      /* Configure the EXTI interrupt using the saved handler */
+      /* Configure the EXTI interrupt using the saved handler to generate
+       * an interrupt when a falling edge is detected on the INT pin.  An
+       * event is also generated (but not used).
+       */
 
       (void)stm32_gpiosetevent(GPIO_MAX3421E_INT, false, true, true,
                                priv->handler, priv->arg);