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NXP S32K1XX EVB boards - clock config cleanup (#556)
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* S32K1XX EVB boards - clock config cleanup

* S32K1XX - Style fix 2
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@jarivanewijk
jarivanewijk authored Mar 12, 2020
1 parent 30b9003 commit 850c7fa
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Showing 10 changed files with 719 additions and 722 deletions.
2 changes: 1 addition & 1 deletion boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
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Expand Up @@ -82,7 +82,7 @@

/* Count of peripheral clock user configurations */

#define NUM_OF_PERIPHERAL_CLOCKS_0 10
#define NUM_OF_PERIPHERAL_CLOCKS_0 11

/****************************************************************************
* Public Types
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179 changes: 85 additions & 94 deletions boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c
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Expand Up @@ -77,132 +77,123 @@ const struct clock_configuration_s g_initial_clkconfig =
{
.scg =
{
.sirc =
.sirc =
{
.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
.initialize = true, /* Initialize */
.stopmode = false, /* SIRCSTEN */
.lowpower = true, /* SIRCLPEN */
.locked = false, /* LK */
.range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
.initialize = true, /* Initialize */
.stopmode = false, /* SIRCSTEN */
.lowpower = true, /* SIRCLPEN */
.locked = false, /* LK */
},
.firc =
.firc =
{
.range = SCG_FIRC_RANGE_48M, /* RANGE */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
.initialize = true, /* Initialize */
.stopmode = false, /* */
.lowpower = false, /* */
.regulator = true, /* FIRCREGOFF */
.locked = false, /* LK */
.range = SCG_FIRC_RANGE_48M, /* RANGE */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
.initialize = true, /* Initialize */
.regulator = true, /* FIRCREGOFF */
.locked = false, /* LK */
},
.sosc =
.sosc =
{
.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
.gain = SCG_SOSC_GAIN_LOW, /* HGO */
.range = SCG_SOSC_RANGE_HIGH, /* RANGE */
.extref = SCG_SOSC_REF_OSC, /* EREFS */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
.initialize = true, /* Initialize */
.stopmode = false, /* */
.lowpower = false, /* */
.locked = false, /* LK */
.mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
.gain = SCG_SOSC_GAIN_LOW, /* HGO */
.range = SCG_SOSC_RANGE_HIGH, /* RANGE */
.extref = SCG_SOSC_REF_OSC, /* EREFS */
.div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
.div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
.initialize = true, /* Initialize */
.locked = false, /* LK */
},
.rtc =
.rtc =
{
.initialize = true, /* Initialize */
.clkin = 0 /* RTC_CLKIN */
.initialize = true, /* Initialize */
.clkin = 0, /* RTC_CLKIN */
},
.clockout =
.clockout =
{
.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
.initialize = true, /* Initialize */
.source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
.initialize = true, /* Initialize */
},
.clockmode =
.clockmode =
{
.rccr = /* RCCR - Run Clock Control Register */
.rccr = /* RCCR - Run Clock Control Register */
{
.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */
.divslow = 2, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1 /* DIVCORE, range 1..16 */
.src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */
.divslow = 2, /* DIVSLOW, range 1..16 */
.divbus = 2, /* DIVBUS, range 1..16 */
.divcore = 1, /* DIVCORE, range 1..16 */
},
.vccr = /* VCCR - VLPR Clock Control Register */
.vccr = /* VCCR - VLPR Clock Control Register */
{
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 1, /* DIVBUS, range 1..16 */
.divcore = 2 /* DIVCORE, range 1..16 */
.src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
.divslow = 4, /* DIVSLOW, range 1..16 */
.divbus = 1, /* DIVBUS, range 1..16 */
.divcore = 2, /* DIVCORE, range 1..16 */
},

/* .altclk */

.initialize = true, /* Initialize */
.initialize = true, /* Initialize */
},
},
.sim =
.sim =
{
.clockout = /* Clock Out configuration. */
{
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
.divider = 1, /* CLKOUTDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = false, /* CLKOUTEN */
},
.lpoclk = /* Low Power Clock configuration. */
.clockout = /* Clock Out configuration. */
{
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
.initialize = true, /* Initialize */
.lpo32k = true, /* LPO32KCLKEN */
.lpo1k = true, /* LPO1KCLKEN */
.source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
.divider = 1, /* CLKOUTDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = false, /* CLKOUTEN */
},
.tclk = /* TCLK CLOCK configuration. */
.lpoclk = /* Low Power Clock configuration. */
{
.tclkfreq[0] = 0, /* TCLK0 */
.tclkfreq[1] = 0, /* TCLK1 */
.tclkfreq[2] = 0, /* TCLK2 */
.initialize = true, /* Initialize */
.rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
.lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
.initialize = true, /* Initialize */
.lpo32k = true, /* LPO32KCLKEN */
.lpo1k = true, /* LPO1KCLKEN */
},
.platgate = /* Platform Gate Clock configuration. */
.tclk = /* TCLK CLOCK configuration. */
{
.initialize = true, /* Initialize */
.mscm = true, /* CGCMSCM */
.mpu = true, /* CGCMPU */
.dma = true, /* CGCDMA */
.erm = true, /* CGCERM */
.eim = true, /* CGCEIM */
.tclkfreq[0] = 0, /* TCLK0 */
.tclkfreq[1] = 0, /* TCLK1 */
.tclkfreq[2] = 0, /* TCLK2 */
.initialize = true, /* Initialize */
},
.traceclk = /* Debug trace Clock Configuration. */
.platgate = /* Platform Gate Clock configuration. */
{
.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
.divider = 1, /* TRACEDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = true, /* TRACEDIVEN */
.fraction = false, /* TRACEFRAC */
.initialize = true, /* Initialize */
.mscm = true, /* CGCMSCM */
.mpu = true, /* CGCMPU */
.dma = true, /* CGCDMA */
.erm = true, /* CGCERM */
.eim = true, /* CGCEIM */
},
#ifdef CONFIG_S32K1XX_HAVE_QSPI
.qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
.traceclk = /* Debug trace Clock Configuration. */
{
.refclk = false, /* Qspi reference clock gating */
.source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
.divider = 1, /* TRACEDIV, range 1..8 */
.initialize = true, /* Initialize */
.enable = true, /* TRACEDIVEN */
.fraction = false, /* TRACEFRAC */
},
#endif
},
.pcc =
.pcc =
{
.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
.pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */
.count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
.pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */
},
.pmc =
.pmc =
{
.lpoclk = /* Low Power Clock configuration. */
.lpoclk = /* Low Power Clock configuration. */
{
.trim = 0, /* Trimming value for LPO */
.initialize = true, /* Initialize */
.enable = true, /* Enable/disable LPO */
.trim = 0, /* Trimming value for LPO */
.initialize = true, /* Initialize */
.enable = true, /* Enable/disable LPO */
},
}
},
};

/****************************************************************************
* Public Functions
****************************************************************************/
115 changes: 57 additions & 58 deletions boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c
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Expand Up @@ -61,14 +61,6 @@
#include "s32k1xx_periphclocks.h"
#include "s32k118evb.h"

/****************************************************************************
* Pre-processor Definitions
****************************************************************************/

/****************************************************************************
* Public Data
****************************************************************************/

/****************************************************************************
* Public Data
****************************************************************************/
Expand All @@ -80,73 +72,80 @@
const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
{
{
.clkname = ADC0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = FLEXCAN0_CLK,
#ifdef CONFIG_S32K1XX_FLEXCAN
.clkgate = true,
#else
.clkgate = false,
#endif
},
{
.clkname = LPI2C0_CLK,
#ifdef CONFIG_S32K1XX_LPI2C0
.clkgate = true,
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
},
{
.clkname = DMAMUX0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = LPSPI0_CLK,
#ifdef CONFIG_S32K1XX_LPSPI0
.clkgate = true,
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
},
{
.clkname = LPTMR0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = LPSPI1_CLK,
#ifdef CONFIG_S32K1XX_LPSPI1
.clkgate = true,
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
},
{
.clkname = LPUART0_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = LPUART0_CLK,
#ifdef CONFIG_S32K1XX_LPUART0
.clkgate = true,
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
},
{
.clkname = LPUART1_CLK,
.clkgate = true,
.clksrc = CLK_SRC_SIRC_DIV2,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = LPUART1_CLK,
#ifdef CONFIG_S32K1XX_LPUART1
.clkgate = true,
#else
.clkgate = false,
#endif
.clksrc = CLK_SRC_SIRC_DIV2,
},
{
.clkname = PORTA_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = PORTA_CLK,
.clkgate = true,
},
{
.clkname = PORTB_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = PORTB_CLK,
.clkgate = true,
},
{
.clkname = PORTC_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = PORTC_CLK,
.clkgate = true,
},
{
.clkname = PORTD_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = PORTD_CLK,
.clkgate = true,
},
{
.clkname = PORTE_CLK,
.clkgate = true,
.clksrc = CLK_SRC_OFF,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
.clkname = PORTE_CLK,
.clkgate = true,
},
};

/****************************************************************************
* Public Functions
****************************************************************************/
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