Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

enabled verilator added test_tb_top, filelist files, common defines, … #81

Merged
merged 1 commit into from
Jan 22, 2021
Merged

enabled verilator added test_tb_top, filelist files, common defines, … #81

merged 1 commit into from
Jan 22, 2021

Commits on Jan 22, 2021

  1. - removed comments from sim.py 

    - removed empty c_sample test from testlist
- added sim.vcd path in test_tb_top
- added verilator tool commands in rtl_simulation.yaml
- added common_defines.vh corresponding to the verilator in the snapshot
folder
- updated tracer.sv;Lint off.
- added filelists corresponding to the verilator
    @amnafayyaz28
    amnafayyaz28 committed Jan 22, 2021
    Configuration menu
    Copy the full SHA
    29840fe View commit details
    Browse the repository at this point in the history