enabled verilator added test_tb_top, filelist files, common defines, … #81
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amnafayyaz28
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Jan 20, 2021
amnafayyaz28
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- Updated test_tb_top.cpp for the sim.vcd path according to the corresponding seed
- Added commands for verilator in rtl_simulation.yaml
- Added test_tb_top.cpp, file lists and common_define files for verilator
- Updated tracer.sv for the warnings in verilator
- Removed unnecessary comments from sim.py and c_sample test from the testlist.yaml
mmhus
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Jan 20, 2021
integration_files/SweRV_EH1/snapshots/default/common_defines_verilator.vh
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haroon-shafique
suggested changes
Jan 21, 2021
- removed empty c_sample test from testlist - added sim.vcd path in test_tb_top - added verilator tool commands in rtl_simulation.yaml - added common_defines.vh corresponding to the verilator in the snapshot folder - updated tracer.sv;Lint off. - added filelists corresponding to the verilator
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haroon-shafique
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Jan 22, 2021
farooqahmed-lm
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Mar 19, 2021
- removed empty c_sample test from testlist - added sim.vcd path in test_tb_top - added verilator tool commands in rtl_simulation.yaml - added common_defines.vh corresponding to the verilator in the snapshot folder - updated tracer.sv;Lint off. - added filelists corresponding to the verilator
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