This project follows my process of building the digital logic for a brainless microprocessor through the use of Digital, a schematic entry tool. We manipulate binary code to navigate data, memory, and instruction sets.
Design testing involves generating test waveform files to show toggling between inputs and their outputs. The designs are ran through Verilog, and waveforms are viewed with GTKWave. The final delivery of the project is a brainless microprocessor that is programmable through the manipulation of the ROM values
We start by building a combinational logic circuit using primitive components.
We will use this component for the Program Counter (PC). The 4-bit incrementor is composed of 4 1-bit adders to accept a 4-bit binary number. This circuit produces a 4-bit binary number and a carry (CRY) output. If CRY is 1, the output number is one more than the 4-bit input.
Half Adder Logic:
| a | b | sum | cry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
A 3-input XOR gate
We need to be able to control the data flow through the circuit using the 4-bit 2-to-1 multiplexer. We also need to create the arithmetic logic unit (ALU) to perform add, sub, negate, etc. and the logical operations.
The microprocessor I'm designing operates on 4-bit numbers, therefore, to accomplish multiplexer behavior on 4-bit numbers, I simply placed four instances of 2-bit muxes (logic table below) and wired up the sel input for the 2-bit muxes from one singular sel signal. Inputs a and b are 4-but buses and are split by bit and wired into each of the 2-bit mux's a inputs. The same concept is applied for b. When sel = 0, the value on a is displayed for the output. When sel = 1, the value of b is passed through to the output.
2-bit-mux logic:
| s | a | b | y |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
This circuit component can perform 2's complement operations, 1's complement operations, or allow input to pass through.
| Invert | Neg | Function |
|---|---|---|
| 0 | 0 | Pass Through |
| 0 | 1 | Pass Through |
| 1 | 0 | 1's complement |
| 1 | 1 | 2's complement |
| Pass | Add | Function |
|---|---|---|
| 0 | 0 | AND |
| 0 | 1 | ADD |
| 1 | 0 | Pass Through |
| 1 | 1 | Pass Through |
A 4-bit storage unit is needed since this microprocessor operates on 4 bits. A 4-bit parallel D register is needed and this will be a component in the CPUs accumulator.
We still need a memory component in order to store instructions and data. The memory for this project has 16 words, with 4 bits each word (4-bit RAM with 16 4-bit words).
The ram_vals.hex file is used to initialize the contents of the RAM. Each line of is read in binary and then loaded into each address in the RAM. A short commented instruction set is inserted as an example
The final part of building the microprocessor involves defining the instruction set for the controller, creating a simple program to insert into the microprocessor's memory, and executing the program.
The memory address generation unit will be able to access memory locations in and out of sequential order. It will either automatically increment memory addresses after each instruction, or change memory locations in order to store or read data. This unit is comprised of a register and incrementor (PC), which will act like the pc, and a memory address register (MAR).
The MAR takes a memory address from the RAM into the data_bus and load_mar is the enable signal to load the memory and push it into the output. When the use_pc is high, the pc values drive the following memory address, when it is low, the MAR content is supplies into the address bus.
The controller will automatically set all of the signals to execute each operation. The Program Ram stores the opcodes that stores operations in hexidecimal form. The ROM is going to be used to decode the instructions and generate all of the signals neededd to operate the CPU according to the instructions. The only other signals that will not be automated will be the clk, reset, and data_in.
Some of the instructions that will be used to test the microcontroller will not be completed in one clock cycle, so this microcontroller will be a ROM-based finite state machine that will be able to break down the opcodes into micro-ops.
The ROM will have preloaded values. The Instruction Register (IR) and the Step Register (SR) combine to form the address inputted to the ROM (4 bits from the IR, and 2 bits from the SR). The Instruction ROM will act as the decoder for the control signals and the programmable logic for the finite-state machine. The inpt for the IR will be the opcode stored inside the Program ROM, and to load it into the IR, the controller has to set the load_ir to 1 (The instruction fetch). The fetch state will begin each of the instructions.
The ROM values willl be loaded from the rom_vals.hex file. The 0x1205 instruction is the hexadecimal value needed to correctly fetch each instruction and the 0x3FFF instruction to force Digital to write out the entires of the ROM when exporting to Digital.
Each component in the microcontroller is a copressed version of all the other components built in parts 1-3.
