UVM Verification Project

Project Overview

This project focuses on the implementation and verification of digital designs using the Universal Verification Methodology (UVM). The project includes a comprehensive testbench environment aimed at ensuring the functionality and performance of various digital components.

Authors

אורי כהן | בר אליס | שון פזרקר | חיים עוזר

Project Report:

Detailed documentation of the UVM Verification process and methodology.

Presentation:

Summary of the project, including key concepts and examples.

How to Read the Files

• Project Report: Open the file דוח UVM Verification - אורי כהן, שון פזרקר, בר אליס, חיים עוזר.pdf using any standard PDF viewer. The report is organized into sections, providing an introduction to UVM, a breakdown of the components used, and a detailed analysis of the verification process.

• Presentation: Open the file מצגת UVM Verification - אורי כהן, שון פזרקר, בר אליס, חיים עוזר.pdf using any standard PDF viewer. The presentation provides a visual overview of the project and can be used for quick reference or presentation purposes.

Acknowledgments

Special thanks to Dr. אביחי אהרון for his guidance and support throughout the project.