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@87flowers
87flowers committed Oct 16, 2024
1 parent a22233a commit 1e5b8cd
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Showing 18 changed files with 222 additions and 226 deletions.
24 changes: 12 additions & 12 deletions src/Sema.zig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23510,7 +23510,7 @@ fn ptrCastFull(
errdefer msg.destroy(sema.gpa);
if (dest_info.flags.size == .Many and
(src_info.flags.size == .Slice or
(src_info.flags.size == .One and Type.fromInterned(src_info.child).zigTypeTag(zcu) == .array)))
(src_info.flags.size == .One and Type.fromInterned(src_info.child).zigTypeTag(zcu) == .array)))
{
try sema.errNote(src, msg, "use 'ptr' field to convert slice to many pointer", .{});
} else {
Expand Down Expand Up @@ -28508,9 +28508,9 @@ fn fieldCallBind(
const first_param_type = Type.fromInterned(func_type.param_types.get(ip)[0]);
if (first_param_type.isGenericPoison() or
(first_param_type.zigTypeTag(zcu) == .pointer and
(first_param_type.ptrSize(zcu) == .One or
first_param_type.ptrSize(zcu) == .C) and
first_param_type.childType(zcu).eql(concrete_ty, zcu)))
(first_param_type.ptrSize(zcu) == .One or
first_param_type.ptrSize(zcu) == .C) and
first_param_type.childType(zcu).eql(concrete_ty, zcu)))
{
// Note that if the param type is generic poison, we know that it must
// specifically be `anytype` since it's the first parameter, meaning we
Expand Down Expand Up @@ -30089,7 +30089,7 @@ fn coerceExtra(

if (dest_info.sentinel == .none or inst_info.sentinel == .none or
Air.internedToRef(dest_info.sentinel) !=
try sema.coerceInMemory(Value.fromInterned(inst_info.sentinel), Type.fromInterned(dest_info.child)))
try sema.coerceInMemory(Value.fromInterned(inst_info.sentinel), Type.fromInterned(dest_info.child)))
break :p;

const slice_ptr = try sema.analyzeSlicePtr(block, inst_src, inst, inst_ty);
Expand Down Expand Up @@ -30923,12 +30923,12 @@ pub fn coerceInMemoryAllowed(
}
const ok_sent = (dest_info.sentinel == null and src_info.sentinel == null) or
(src_info.sentinel != null and
dest_info.sentinel != null and
dest_info.sentinel.?.eql(
try pt.getCoerced(src_info.sentinel.?, dest_info.elem_type),
dest_info.elem_type,
zcu,
));
dest_info.sentinel != null and
dest_info.sentinel.?.eql(
try pt.getCoerced(src_info.sentinel.?, dest_info.elem_type),
dest_info.elem_type,
zcu,
));
if (!ok_sent) {
return InMemoryCoercionResult{ .array_sentinel = .{
.actual = src_info.sentinel orelse Value.@"unreachable",
Expand Down Expand Up @@ -31341,7 +31341,7 @@ fn coerceInMemoryAllowedPtrs(

const ok_sent = dest_info.sentinel == .none or src_info.flags.size == .C or
(src_info.sentinel != .none and
dest_info.sentinel == try zcu.intern_pool.getCoerced(sema.gpa, pt.tid, src_info.sentinel, dest_info.child));
dest_info.sentinel == try zcu.intern_pool.getCoerced(sema.gpa, pt.tid, src_info.sentinel, dest_info.child));
if (!ok_sent) {
return InMemoryCoercionResult{ .ptr_sentinel = .{
.actual = switch (src_info.sentinel) {
Expand Down
11 changes: 6 additions & 5 deletions src/Type.zig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -614,11 +614,12 @@ pub fn hasRuntimeBitsInner(
// in which case we want control flow to continue down below.
if (tag_ty != .none and
try Type.fromInterned(tag_ty).hasRuntimeBitsInner(
ignore_comptime_only,
strat,
zcu,
tid,
)) {
ignore_comptime_only,
strat,
zcu,
tid,
))
{
return true;
}
},
Expand Down
8 changes: 4 additions & 4 deletions src/Zcu.zig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1195,8 +1195,8 @@ pub const SrcLoc = struct {
const case = tree.fullSwitchCase(case_node).?;
const is_special = (case.ast.values.len == 0) or
(case.ast.values.len == 1 and
node_tags[case.ast.values[0]] == .identifier and
mem.eql(u8, tree.tokenSlice(main_tokens[case.ast.values[0]]), "_"));
node_tags[case.ast.values[0]] == .identifier and
mem.eql(u8, tree.tokenSlice(main_tokens[case.ast.values[0]]), "_"));
if (!is_special) continue;

return tree.nodeToSpan(case_node);
Expand All @@ -1215,8 +1215,8 @@ pub const SrcLoc = struct {
const case = tree.fullSwitchCase(case_node).?;
const is_special = (case.ast.values.len == 0) or
(case.ast.values.len == 1 and
node_tags[case.ast.values[0]] == .identifier and
mem.eql(u8, tree.tokenSlice(main_tokens[case.ast.values[0]]), "_"));
node_tags[case.ast.values[0]] == .identifier and
mem.eql(u8, tree.tokenSlice(main_tokens[case.ast.values[0]]), "_"));
if (is_special) continue;

for (case.ast.values) |item_node| {
Expand Down
21 changes: 10 additions & 11 deletions src/arch/riscv64/CodeGen.zig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -684,8 +684,7 @@ fn restoreState(func: *Func, state: State, deaths: []const Air.Inst.Index, compt

const ExpectedContents = [@typeInfo(RegisterManager.TrackedRegisters).array.len]RegisterLock;
var stack align(@max(@alignOf(ExpectedContents), @alignOf(std.heap.StackFallbackAllocator(0)))) =
if (opts.update_tracking)
{} else std.heap.stackFallback(@sizeOf(ExpectedContents), func.gpa);
if (opts.update_tracking) {} else std.heap.stackFallback(@sizeOf(ExpectedContents), func.gpa);

var reg_locks = if (opts.update_tracking) {} else try std.ArrayList(RegisterLock).initCapacity(
stack.get(),
Expand Down Expand Up @@ -2305,7 +2304,7 @@ fn airIntCast(func: *Func, inst: Air.Inst.Index) !void {

const dst_mcv = if (dst_int_info.bits <= src_storage_bits and
math.divCeil(u16, dst_int_info.bits, 64) catch unreachable ==
math.divCeil(u32, src_storage_bits, 64) catch unreachable and
math.divCeil(u32, src_storage_bits, 64) catch unreachable and
func.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {
const dst_mcv = try func.allocRegOrMem(dst_ty, inst, true);
try func.genCopy(min_ty, dst_mcv, src_mcv);
Expand Down Expand Up @@ -2363,9 +2362,9 @@ fn airNot(func: *Func, inst: Air.Inst.Index) !void {

const dst_reg: Register =
if (func.reuseOperand(inst, ty_op.operand, 0, operand) and operand == .register)
operand.register
else
(try func.allocRegOrMem(func.typeOfIndex(inst), inst, true)).register;
operand.register
else
(try func.allocRegOrMem(func.typeOfIndex(inst), inst, true)).register;

switch (ty.zigTypeTag(zcu)) {
.bool => {
Expand Down Expand Up @@ -6273,11 +6272,11 @@ fn airAsm(func: *Func, inst: Air.Inst.Index) !void {

const instruction: union(enum) { mnem: Mnemonic, pseudo: Pseudo } =
if (std.meta.stringToEnum(Mnemonic, mnem_str)) |mnem|
.{ .mnem = mnem }
else if (std.meta.stringToEnum(Pseudo, mnem_str)) |pseudo|
.{ .pseudo = pseudo }
else
return func.fail("invalid mnem str '{s}'", .{mnem_str});
.{ .mnem = mnem }
else if (std.meta.stringToEnum(Pseudo, mnem_str)) |pseudo|
.{ .pseudo = pseudo }
else
return func.fail("invalid mnem str '{s}'", .{mnem_str});

const Operand = union(enum) {
none,
Expand Down
65 changes: 32 additions & 33 deletions src/arch/x86_64/CodeGen.zig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2921,8 +2921,7 @@ fn restoreState(self: *Self, state: State, deaths: []const Air.Inst.Index, compt

const ExpectedContents = [@typeInfo(RegisterManager.TrackedRegisters).array.len]RegisterLock;
var stack align(@max(@alignOf(ExpectedContents), @alignOf(std.heap.StackFallbackAllocator(0)))) =
if (opts.update_tracking)
{} else std.heap.stackFallback(@sizeOf(ExpectedContents), self.gpa);
if (opts.update_tracking) {} else std.heap.stackFallback(@sizeOf(ExpectedContents), self.gpa);

var reg_locks = if (opts.update_tracking) {} else try std.ArrayList(RegisterLock).initCapacity(
stack.get(),
Expand Down Expand Up @@ -3490,7 +3489,7 @@ fn airIntCast(self: *Self, inst: Air.Inst.Index) !void {

const dst_mcv = if (dst_int_info.bits <= src_storage_bits and
math.divCeil(u16, dst_int_info.bits, 64) catch unreachable ==
math.divCeil(u32, src_storage_bits, 64) catch unreachable and
math.divCeil(u32, src_storage_bits, 64) catch unreachable and
self.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: {
const dst_mcv = try self.allocRegOrMem(inst, true);
try self.genCopy(min_ty, dst_mcv, src_mcv, .{});
Expand Down Expand Up @@ -5025,10 +5024,10 @@ fn genIntMulDivOpMir(self: *Self, tag: Mir.Inst.FixedTag, ty: Type, lhs: MCValue
._ => {
const hi_reg: Register =
switch (bit_size) {
8 => .ah,
16, 32, 64 => .edx,
else => unreachable,
};
8 => .ah,
16, 32, 64 => .edx,
else => unreachable,
};
try self.asmRegisterRegister(.{ ._, .xor }, hi_reg, hi_reg);
},
.i_ => try self.asmOpOnly(.{ ._, switch (bit_size) {
Expand Down Expand Up @@ -9352,9 +9351,9 @@ fn genShiftBinOpMir(
.size = Memory.Size.fromSize(abi_size),
.disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse
return self.fail("TODO genShiftBinOpMir between {s} and {s}", .{
@tagName(lhs_mcv),
@tagName(shift_mcv),
}),
@tagName(lhs_mcv),
@tagName(shift_mcv),
}),
} },
},
.indirect => |reg_off| .{
Expand Down Expand Up @@ -10084,17 +10083,17 @@ fn genBinOp(

const ordered_air: [2]Air.Inst.Ref = if (lhs_ty.isVector(zcu) and
switch (lhs_ty.childType(zcu).zigTypeTag(zcu)) {
.bool => false,
.int => switch (air_tag) {
.cmp_lt, .cmp_gte => true,
else => false,
},
.float => switch (air_tag) {
.cmp_gte, .cmp_gt => true,
else => false,
},
else => unreachable,
}) .{ rhs_air, lhs_air } else .{ lhs_air, rhs_air };
.bool => false,
.int => switch (air_tag) {
.cmp_lt, .cmp_gte => true,
else => false,
},
.float => switch (air_tag) {
.cmp_gte, .cmp_gt => true,
else => false,
},
else => unreachable,
}) .{ rhs_air, lhs_air } else .{ lhs_air, rhs_air };

if (lhs_ty.isAbiInt(zcu)) for (ordered_air) |op_air| {
switch (try self.resolveInst(op_air)) {
Expand Down Expand Up @@ -12069,13 +12068,13 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
.size = Memory.Size.fromSize(abi_size),
.disp = math.cast(i32, @as(i64, @bitCast(addr))) orelse
return self.asmRegisterRegister(
.{ .i_, .mul },
dst_alias,
registerAlias(
try self.copyToTmpRegister(dst_ty, resolved_src_mcv),
abi_size,
.{ .i_, .mul },
dst_alias,
registerAlias(
try self.copyToTmpRegister(dst_ty, resolved_src_mcv),
abi_size,
),
),
),
} },
},
.indirect => |reg_off| .{
Expand Down Expand Up @@ -14168,9 +14167,9 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
mem.eql(u8, rest, "r,m") or mem.eql(u8, rest, "m,r"))
self.register_manager.tryAllocReg(maybe_inst, abi.RegisterClass.gp) orelse
if (output != .none)
null
else
return self.fail("ran out of registers lowering inline asm", .{})
null
else
return self.fail("ran out of registers lowering inline asm", .{})
else if (mem.startsWith(u8, rest, "{") and mem.endsWith(u8, rest, "}"))
parseRegName(rest["{".len .. rest.len - "}".len]) orelse
return self.fail("invalid register constraint: '{s}'", .{constraint})
Expand Down Expand Up @@ -16610,9 +16609,9 @@ fn airAtomicLoad(self: *Self, inst: Air.Inst.Index) !void {

const dst_mcv =
if (self.reuseOperand(inst, atomic_load.ptr, 0, ptr_mcv))
ptr_mcv
else
try self.allocRegOrMem(inst, true);
ptr_mcv
else
try self.allocRegOrMem(inst, true);

try self.load(dst_mcv, ptr_ty, ptr_mcv);
return self.finishAir(inst, dst_mcv, .{ atomic_load.ptr, .none, .none });
Expand Down
38 changes: 19 additions & 19 deletions src/arch/x86_64/Lower.zig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -418,17 +418,17 @@ fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand)
_ = lower.reloc(.{ .linker_tlsld = sym_index }, 0);
lower.result_insts[lower.result_insts_len] =
try Instruction.new(.none, .lea, &[_]Operand{
.{ .reg = .rdi },
.{ .mem = Memory.initRip(mem_op.sib.ptr_size, 0) },
});
.{ .reg = .rdi },
.{ .mem = Memory.initRip(mem_op.sib.ptr_size, 0) },
});
lower.result_insts_len += 1;
_ = lower.reloc(.{
.linker_extern_fn = try elf_file.getGlobalSymbol("__tls_get_addr", null),
}, 0);
lower.result_insts[lower.result_insts_len] =
try Instruction.new(.none, .call, &[_]Operand{
.{ .imm = Immediate.s(0) },
});
.{ .imm = Immediate.s(0) },
});
lower.result_insts_len += 1;
_ = lower.reloc(.{ .linker_dtpoff = sym_index }, 0);
emit_mnemonic = .lea;
Expand All @@ -440,9 +440,9 @@ fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand)
// Since we are linking statically, we emit LE model directly.
lower.result_insts[lower.result_insts_len] =
try Instruction.new(.none, .mov, &[_]Operand{
.{ .reg = .rax },
.{ .mem = Memory.initSib(.qword, .{ .base = .{ .reg = .fs } }) },
});
.{ .reg = .rax },
.{ .mem = Memory.initSib(.qword, .{ .base = .{ .reg = .fs } }) },
});
lower.result_insts_len += 1;
_ = lower.reloc(.{ .linker_reloc = sym_index }, 0);
emit_mnemonic = .lea;
Expand All @@ -464,9 +464,9 @@ fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand)
const reg = ops[0].reg;
lower.result_insts[lower.result_insts_len] =
try Instruction.new(.none, .mov, &[_]Operand{
.{ .reg = reg.to64() },
.{ .mem = Memory.initRip(.qword, 0) },
});
.{ .reg = reg.to64() },
.{ .mem = Memory.initRip(.qword, 0) },
});
lower.result_insts_len += 1;
break :op .{ .mem = Memory.initSib(mem_op.sib.ptr_size, .{ .base = .{
.reg = reg.to64(),
Expand Down Expand Up @@ -496,14 +496,14 @@ fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand)
_ = lower.reloc(.{ .linker_reloc = sym_index }, 0);
lower.result_insts[lower.result_insts_len] =
try Instruction.new(.none, .mov, &[_]Operand{
.{ .reg = .rdi },
.{ .mem = Memory.initRip(mem_op.sib.ptr_size, 0) },
});
.{ .reg = .rdi },
.{ .mem = Memory.initRip(mem_op.sib.ptr_size, 0) },
});
lower.result_insts_len += 1;
lower.result_insts[lower.result_insts_len] =
try Instruction.new(.none, .call, &[_]Operand{
.{ .mem = Memory.initSib(.qword, .{ .base = .{ .reg = .rdi } }) },
});
.{ .mem = Memory.initSib(.qword, .{ .base = .{ .reg = .rdi } }) },
});
lower.result_insts_len += 1;
emit_mnemonic = .mov;
break :op .{ .reg = .rax };
Expand All @@ -520,9 +520,9 @@ fn emit(lower: *Lower, prefix: Prefix, mnemonic: Mnemonic, ops: []const Operand)
const reg = ops[0].reg;
lower.result_insts[lower.result_insts_len] =
try Instruction.new(.none, .mov, &[_]Operand{
.{ .reg = reg.to64() },
.{ .mem = Memory.initRip(.qword, 0) },
});
.{ .reg = reg.to64() },
.{ .mem = Memory.initRip(.qword, 0) },
});
lower.result_insts_len += 1;
break :op .{ .mem = Memory.initSib(mem_op.sib.ptr_size, .{ .base = .{
.reg = reg.to64(),
Expand Down
2 changes: 1 addition & 1 deletion src/codegen.zig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -452,7 +452,7 @@ pub fn generateSymbol(

const padding = abi_size -
(math.cast(usize, Type.fromInterned(vector_type.child).abiSize(zcu) * vector_type.len) orelse
return error.Overflow);
return error.Overflow);
if (padding > 0) try code.appendNTimes(0, padding);
}
},
Expand Down
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