ComputerArchitecture

Pipeline CPU on FPGA Final Project for CA 2014 Fall

Name		Name	Last commit message	Last commit date
Latest commit History 38 Commits
unit test		unit test
.DS_Store		.DS_Store
README.md		README.md
alu.vhd		alu.vhd
clock.vhd		clock.vhd
com.vhd		com.vhd
controller.vhd		controller.vhd
ex_forward.vhd		ex_forward.vhd
ex_me_reg.vhd		ex_me_reg.vhd
hazard.vhd		hazard.vhd
id_ex_reg.vhd		id_ex_reg.vhd
id_forward.vhd		id_forward.vhd
if_id_reg.vhd		if_id_reg.vhd
im_controller.vhd		im_controller.vhd
inst_set.xlsx		inst_set.xlsx
me_wb_reg.vhd		me_wb_reg.vhd
partpipe.vhd		partpipe.vhd
pc.vhd		pc.vhd
pipeline.ucf		pipeline.ucf
pipeline.vhd		pipeline.vhd
pipeline_tb.vhd		pipeline_tb.vhd
pipline_v3.pdf		pipline_v3.pdf
reg_file.vhd		reg_file.vhd
reg_file.vhd.bak		reg_file.vhd.bak
sram_controller.vhd		sram_controller.vhd

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