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Display statements are removed during synthesis #98

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merged 2 commits into from
Nov 8, 2023
Merged

Display statements are removed during synthesis #98

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f092ad9
Display statements are removed during synthesis
Nov 8, 2023
130ac10
Redirect to stable state from default case
Nov 8, 2023
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66 changes: 61 additions & 5 deletions utils/rtl/tl2umi_np.v
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Original file line number Diff line number Diff line change
Expand Up @@ -318,8 +318,20 @@ module tl2umi_np #(
put_bytes_resp <= dataag_out_resp_bytes;
end
else begin
// Not supported request, ignore
// Not supported response type. Ignore and stay in idle.
resp_state <= RESP_IDLE;
dataag_out_resp_ready_assert <= 1'b1;
tl_d_valid <= 1'b0;
tl_d_opcode <= 3'b0;
tl_d_size <= 3'b0;
tl_d_source <= 5'b0;
tl_d_data <= 64'b0;
put_ack_resp <= 1'b0;
put_bytes_resp <= 8'b0;
get_ack_resp <= 1'b0;
`ifndef SYNTHESIS
$display("Unsupported response on UMI side %d", dataag_out_resp_cmd_opcode);
`endif
end
end
end
Expand Down Expand Up @@ -381,8 +393,20 @@ module tl2umi_np #(
end
end
default: begin
// Entered wrong state
// Entered wrong state. Return to idle.
resp_state <= RESP_IDLE;
dataag_out_resp_ready_assert <= 1'b1;
tl_d_valid <= 1'b0;
tl_d_opcode <= 3'b0;
tl_d_size <= 3'b0;
tl_d_source <= 5'b0;
tl_d_data <= 64'b0;
put_ack_resp <= 1'b0;
put_bytes_resp <= 8'b0;
get_ack_resp <= 1'b0;
`ifndef SYNTHESIS
$display("Entered Invalid State in Response State Machine");
`endif
end

endcase
Expand Down Expand Up @@ -526,7 +550,7 @@ module tl2umi_np #(

always @(posedge clk or negedge nreset) begin
if (~nreset) begin
req_state <= 'b0;
req_state <= REQ_IDLE;
tl_a_ready_assert <= 1'b1;
uhost_req_packet_cmd_opcode <= 'b0;
uhost_req_packet_cmd_len <= 'b0;
Expand All @@ -538,6 +562,7 @@ module tl2umi_np #(
uhost_req_packet_data <= 'b0;
uhost_req_packet_valid_r <= 1'b0;
ml_tx_non_zero_mask_r <= 1'b0;
put_ack_req <= 1'b0;
put_bytes_req <= 8'b0;
end
else begin
Expand Down Expand Up @@ -628,8 +653,23 @@ module tl2umi_np #(
endcase
end
default: begin
// Not supported request, ignore
// Not supported request type. Ignore and stay in idle.
req_state <= REQ_IDLE;
tl_a_ready_assert <= 1'b1;
uhost_req_packet_cmd_opcode <= 'b0;
uhost_req_packet_cmd_len <= 'b0;
uhost_req_packet_cmd_size <= 'b0;
uhost_req_packet_cmd_atype <= 'b0;
uhost_req_packet_cmd_eom <= 'b0;
uhost_req_packet_dstaddr <= 'b0;
uhost_req_packet_srcaddr <= 'b0;
uhost_req_packet_data <= 'b0;
uhost_req_packet_valid_r <= 1'b0;
ml_tx_non_zero_mask_r <= 1'b0;
put_bytes_req <= 8'b0;
`ifndef SYNTHESIS
$display("Unsupported request on TL side %d", tl_a_opcode);
`endif
end
endcase
end
Expand Down Expand Up @@ -693,8 +733,24 @@ module tl2umi_np #(
end
end
default: begin
// Entered wrong state
// Entered wrong state. Return to idle.
req_state <= REQ_IDLE;
tl_a_ready_assert <= 1'b1;
uhost_req_packet_cmd_opcode <= 'b0;
uhost_req_packet_cmd_len <= 'b0;
uhost_req_packet_cmd_size <= 'b0;
uhost_req_packet_cmd_atype <= 'b0;
uhost_req_packet_cmd_eom <= 'b0;
uhost_req_packet_dstaddr <= 'b0;
uhost_req_packet_srcaddr <= 'b0;
uhost_req_packet_data <= 'b0;
uhost_req_packet_valid_r <= 1'b0;
ml_tx_non_zero_mask_r <= 1'b0;
put_ack_req <= 1'b0;
put_bytes_req <= 8'b0;
`ifndef SYNTHESIS
$display("Entered Invalid State in Request State Machine");
`endif
end

endcase
Expand Down
18 changes: 15 additions & 3 deletions utils/rtl/umi2tl_np.v
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Original file line number Diff line number Diff line change
Expand Up @@ -270,7 +270,11 @@ module umi2tl_np #(
tl_a_opcode_r <= `TL_OP_LogicalData;
end
end
default: $display("[UMI2TL]: Unsupported UMI Request");
`ifndef SYNTHESIS
default: begin
$display("[UMI2TL]: Unsupported UMI Request");
end
`endif
endcase
end
end
Expand All @@ -293,7 +297,11 @@ module umi2tl_np #(
UMI_REQ_ATOMICMAXU: tl_a_param_r <= `TL_PA_MAXU;
UMI_REQ_ATOMICMINU: tl_a_param_r <= `TL_PA_MINU;
UMI_REQ_ATOMICSWAP: tl_a_param_r <= `TL_PL_SWAP;
default: $display("[UMI2TL]: Unsupported UMI Atomic");
`ifndef SYNTHESIS
default: begin
$display("[UMI2TL]: Unsupported UMI Atomic");
end
`endif
endcase
end
else begin
Expand Down Expand Up @@ -458,7 +466,11 @@ module umi2tl_np #(
case (tl_d_opcode)
`TL_OP_AccessAck: udev_resp_cmd_opcode_r <= UMI_RESP_WRITE;
`TL_OP_AccessAckData: udev_resp_cmd_opcode_r <= UMI_RESP_READ;
default: $display("[UMI2TL]: Unsupported TileLink Response");
`ifndef SYNTHESIS
default: begin
$display("[UMI2TL]: Unsupported TileLink Response");
end
`endif
endcase
end
end
Expand Down