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Renaming umi_port module as umi_mux #159

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merged 4 commits into from
Aug 27, 2024
Merged

Renaming umi_port module as umi_mux #159

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18c01ac
Renaming umi_port module as umi_mux
aolofsson Aug 27, 2024
c21e1fb
Update umi_mux in umi_ram
azaidy Aug 27, 2024
790bf3c
Disable tracing
azaidy Aug 27, 2024
97a18e0
Update umi_mux in lumi_tx
azaidy Aug 27, 2024
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14 changes: 12 additions & 2 deletions umi/lumi/rtl/lumi_tx.v
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Original file line number Diff line number Diff line change
Expand Up @@ -245,13 +245,19 @@ module lumi_tx
//# UMI Transmit Arbiter
//########################################

// TODO: umi_mux should be changed as follows:
// .arbmode (2'b00),
// .umi_in_valid ({umi_req_in_gated,umi_resp_in_gated}),

// Mux together response and request over one data channel
// the mux assumes one hot select (valid so need to prioritize the resp)
/*umi_mux AUTO_TEMPLATE(
.arbmode (2'b10),
.arbmask ({2{1'b0}}),
.umi_out_ready (lumi_txrdy & ~(|crdt_updt_send)),
.umi_out_valid (),
.umi_in_ready ({umi_req_ready,umi_resp_ready}),
.umi_in_valid ({umi_req_in_gated & ~umi_resp_in_gated ,umi_resp_in_gated}),
.umi_in_valid ({umi_req_in_gated & ~umi_resp_in_gated,umi_resp_in_gated}),
.umi_in_cmd ({umi_req_in_cmd,umi_resp_in_cmd}),
.umi_in_\(.*\)addr ({umi_req_in_\1addr,umi_resp_in_\1addr}),
.umi_in_data ({umi_req_in_data,umi_resp_in_data}),
Expand All @@ -270,7 +276,11 @@ module lumi_tx
.umi_out_srcaddr (umi_out_srcaddr[AW-1:0]),
.umi_out_data (umi_out_data[DW-1:0]),
// Inputs
.umi_in_valid ({umi_req_in_gated & ~umi_resp_in_gated ,umi_resp_in_gated}), // Templated
.clk (clk),
.nreset (nreset),
.arbmode (2'b10),
.arbmask ({2{1'b0}}),
.umi_in_valid ({umi_req_in_gated & ~umi_resp_in_gated,umi_resp_in_gated}), // Templated
.umi_in_cmd ({umi_req_in_cmd,umi_resp_in_cmd}), // Templated
.umi_in_dstaddr ({umi_req_in_dstaddr,umi_resp_in_dstaddr}), // Templated
.umi_in_srcaddr ({umi_req_in_srcaddr,umi_resp_in_srcaddr}), // Templated
Expand Down
140 changes: 92 additions & 48 deletions umi/sumi/rtl/umi_mux.v
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright 2020 Zero ASIC Corporation
* Copyright 2024 Zero ASIC Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand All @@ -15,70 +15,114 @@
*
* ----
*
* ##Documentation##
*
* - Selects between N inputs
* - Assumes one-hot selects
* - WARNING: input ready is combinatorially connected to the output ready.
* N:1 UMI transaction mux with arbiter and flow control.
*
******************************************************************************/



module umi_mux
#(parameter DW = 256, // UMI transaction width
parameter CW = 32,
parameter AW = 64,
parameter N = 4 // number of inputs
#(parameter N = 2, // mumber of inputs
parameter DW = 128, // umi data width
parameter CW = 32, // umi command width
parameter AW = 6 // umi address width
)
(// Incoming UMI
input [N-1:0] umi_in_valid,
input [N*CW-1:0] umi_in_cmd,
input [N*AW-1:0] umi_in_dstaddr,
input [N*AW-1:0] umi_in_srcaddr,
input [N*DW-1:0] umi_in_data,
output [N-1:0] umi_in_ready,
// Outgoing UMI
output umi_out_valid,
input umi_out_ready,
output [CW-1:0] umi_out_cmd,
output [AW-1:0] umi_out_dstaddr,
output [AW-1:0] umi_out_srcaddr,
output [DW-1:0] umi_out_data
(// controls
input clk,
input nreset,
input [1:0] arbmode, // arbiter` mode (0=fixed)
input [N-1:0] arbmask, // arbiter mask (0=fixed)
// incoming UMI
input [N-1:0] umi_in_valid,
input [N*CW-1:0] umi_in_cmd,
input [N*AW-1:0] umi_in_dstaddr,
input [N*AW-1:0] umi_in_srcaddr,
input [N*DW-1:0] umi_in_data,
output reg [N-1:0] umi_in_ready,
// outgoing UMI
output umi_out_valid,
output [CW-1:0] umi_out_cmd,
output [AW-1:0] umi_out_dstaddr,
output [AW-1:0] umi_out_srcaddr,
output [DW-1:0] umi_out_data,
input umi_out_ready
);

// valid output
assign umi_out_valid = |umi_in_valid[N-1:0];
wire [N*N-1:0] grants;

//##############################
// Valid Arbiter
//##############################

umi_arbiter #(.N(N))
umi_arbiter (// Outputs
.grants (grants[N-1:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.mode (arbmode[1:0]),
.mask (arbmask[N-1:0]),
.requests (umi_in_valid[N-1:0]));

assign umi_out_valid = |grants[N-1:0];

//##############################
// Ready
//##############################


// valid[j] | out_ready[j] | grant[j] | in_ready
//------------------------------------------------
// 0 x x | 1
// 1 0 x | 0
// 1 1 0 | 0
// 1 1 1 | 1

// ready pusback
assign umi_in_ready[N-1:0] = {N{umi_out_ready}};
integer j;
always @(*)
begin
umi_in_ready[N-1:0] = {N{1'b1}};
for (j=0;j<N;j=j+1)
umi_in_ready[j] = umi_in_ready[j] & ~(umi_in_valid[j] &
(~grants[j] | ~umi_out_ready));
end

// packet mux
//##############################
// Output Mux
//##############################

// data
la_vmux #(.N(N),
.W(CW))
la_cmd_vmux(.out (umi_out_cmd[CW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_cmd[N*CW-1:0]));
.W(DW))
la_data_vmux(// Outputs
.out (umi_out_data[DW-1:0]),
// Inputs
.sel (grants[N-1:0]),
.in (umi_in_data[N*DW-1:0]));

// packet mux
// srcaddr
la_vmux #(.N(N),
.W(AW))
la_dstaddr_vmux(.out (umi_out_dstaddr[AW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_dstaddr[N*AW-1:0]));
la_src_vmux(// Outputs
.out (umi_out_srcaddr[AW-1:0]),
// Inputs
.sel (grants[N-1:0]),
.in (umi_in_srcaddr[N*AW-1:0]));

// packet mux
// dstaddr
la_vmux #(.N(N),
.W(AW))
la_srcaddr_vmux(.out (umi_out_srcaddr[AW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_srcaddr[N*AW-1:0]));
la_dst_vmux(// Outputs
.out (umi_out_dstaddr[AW-1:0]),
// Inputs
.sel (grants[N-1:0]),
.in (umi_in_dstaddr[N*AW-1:0]));

// packet mux
// command
la_vmux #(.N(N),
.W(DW))
la_data_vmux(.out (umi_out_data[DW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_data[N*DW-1:0]));
.W(CW))
la_cmd_vmux(// Outputs
.out (umi_out_cmd[CW-1:0]),
// Inputs
.sel (grants[N-1:0]),
.in (umi_in_cmd[N*CW-1:0]));

endmodule
84 changes: 84 additions & 0 deletions umi/sumi/rtl/umi_mux_old.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,84 @@
/*******************************************************************************
* Copyright 2020 Zero ASIC Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----
*
* ##Documentation##
*
* - Selects between N inputs
* - Assumes one-hot selects
* - WARNING: input ready is combinatorially connected to the output ready.
*
******************************************************************************/



module umi_mux_old
#(parameter DW = 256, // UMI transaction width
parameter CW = 32,
parameter AW = 64,
parameter N = 4 // number of inputs
)
(// Incoming UMI
input [N-1:0] umi_in_valid,
input [N*CW-1:0] umi_in_cmd,
input [N*AW-1:0] umi_in_dstaddr,
input [N*AW-1:0] umi_in_srcaddr,
input [N*DW-1:0] umi_in_data,
output [N-1:0] umi_in_ready,
// Outgoing UMI
output umi_out_valid,
input umi_out_ready,
output [CW-1:0] umi_out_cmd,
output [AW-1:0] umi_out_dstaddr,
output [AW-1:0] umi_out_srcaddr,
output [DW-1:0] umi_out_data
);

// valid output
assign umi_out_valid = |umi_in_valid[N-1:0];

// ready pusback
assign umi_in_ready[N-1:0] = {N{umi_out_ready}};

// packet mux
la_vmux #(.N(N),
.W(CW))
la_cmd_vmux(.out (umi_out_cmd[CW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_cmd[N*CW-1:0]));

// packet mux
la_vmux #(.N(N),
.W(AW))
la_dstaddr_vmux(.out (umi_out_dstaddr[AW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_dstaddr[N*AW-1:0]));

// packet mux
la_vmux #(.N(N),
.W(AW))
la_srcaddr_vmux(.out (umi_out_srcaddr[AW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_srcaddr[N*AW-1:0]));

// packet mux
la_vmux #(.N(N),
.W(DW))
la_data_vmux(.out (umi_out_data[DW-1:0]),
.sel (umi_in_valid[N-1:0]),
.in (umi_in_data[N*DW-1:0]));

endmodule
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