Resolving reviewer comments

zeroasiccorp · Jan 22, 2025 · 329dcbd · 329dcbd
1 parent 4ca08ec
commit 329dcbd
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Showing 2 changed files with 29 additions and 29 deletions.
diff --git a/umi/sumi/testbench/testbench_regif.sv b/umi/sumi/testbench/testbench_regif.sv
@@ -1,4 +1,4 @@
-/*******************************************************************************
+/**************************************************************************
  * Copyright 2020 Zero ASIC Corporation
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -18,7 +18,7 @@
  * Documentation:
  * - Simple register interface testbench
  *
- ******************************************************************************/
+ *************************************************************************/
 `default_nettype none
 
 module testbench (
@@ -126,34 +126,34 @@ module testbench (
                .AW(AW),
                .DW(DW),
                .RW(RW))
-   umi_regif(.reg_ready       (1'b1),
-               .reg_err         (2'b0),
-               /*AUTOINST*/
-               // Outputs
-               .udev_req_ready  (udev_req_ready),
-               .udev_resp_valid (udev_resp_valid),
-               .udev_resp_cmd   (udev_resp_cmd[CW-1:0]),
-               .udev_resp_dstaddr(udev_resp_dstaddr[AW-1:0]),
-               .udev_resp_srcaddr(udev_resp_srcaddr[AW-1:0]),
-               .udev_resp_data  (udev_resp_data[DW-1:0]),
-               .reg_write       (reg_write),
-               .reg_read        (reg_read),
-               .reg_addr        (reg_addr[AW-1:0]),
-               .reg_wrdata      (reg_wrdata[RW-1:0]),
-               .reg_prot        (reg_prot[1:0]),
-               // Inputs
-               .clk             (clk),
-               .nreset          (nreset),
-               .udev_req_valid  (udev_req_valid & initdone), // Templated
-               .udev_req_cmd    (udev_req_cmd[CW-1:0]),
-               .udev_req_dstaddr(udev_req_dstaddr[AW-1:0]),
-               .udev_req_srcaddr(udev_req_srcaddr[AW-1:0]),
-               .udev_req_data   (udev_req_data[DW-1:0]),
-               .udev_resp_ready (udev_resp_ready & initdone), // Templated
-               .reg_rddata      (reg_rddata[RW-1:0]));
+   umi_regif(.reg_ready       (1'b1), // no bw to test for this rare feature
+             .reg_err         (2'b0), // TODO: implement when needed
+             /*AUTOINST*/
+             // Outputs
+             .udev_req_ready    (udev_req_ready),
+             .udev_resp_valid   (udev_resp_valid),
+             .udev_resp_cmd     (udev_resp_cmd[CW-1:0]),
+             .udev_resp_dstaddr (udev_resp_dstaddr[AW-1:0]),
+             .udev_resp_srcaddr (udev_resp_srcaddr[AW-1:0]),
+             .udev_resp_data    (udev_resp_data[DW-1:0]),
+             .reg_write         (reg_write),
+             .reg_read          (reg_read),
+             .reg_addr          (reg_addr[AW-1:0]),
+             .reg_wrdata        (reg_wrdata[RW-1:0]),
+             .reg_prot          (reg_prot[1:0]),
+             // Inputs
+             .clk               (clk),
+             .nreset            (nreset),
+             .udev_req_valid    (udev_req_valid & initdone), // Templated
+             .udev_req_cmd      (udev_req_cmd[CW-1:0]),
+             .udev_req_dstaddr  (udev_req_dstaddr[AW-1:0]),
+             .udev_req_srcaddr  (udev_req_srcaddr[AW-1:0]),
+             .udev_req_data     (udev_req_data[DW-1:0]),
+             .udev_resp_ready   (udev_resp_ready & initdone), // Templated
+             .reg_rddata        (reg_rddata[RW-1:0]));
 
    ///////////////////////////////////////////
-   // Support circutry
+   // Support circuitry
    ///////////////////////////////////////////
 
    // Register array

diff --git a/umi/sumi/tests/conftest.py b/umi/sumi/tests/conftest.py
@@ -27,7 +27,7 @@ def sumi_dut(build_dir, request):
     }
 
     dut = SbDut('testbench', cmdline=True, extra_args=extra_args,
-                default_main=True, trace_type='fst', trace=True)
+                default_main=True)
 
     dut.use(sumi)