switchboard 0.0.17 SB-447 SB-450 SB-451 SB-452

examples/dependencies.json

@@ -2,7 +2,7 @@
     {
         "name": "umi",
         "url": "git@github.com:zeroasiccorp/umi.git",
-        "commit": "f85d0cc"
+        "commit": "6bd33a1"
     },
     {
         "name": "old-umi",
@@ -12,7 +12,7 @@
     {
         "name": "lambdalib",
         "url": "git@github.com:siliconcompiler/lambdalib.git",
-        "commit": "ebbcd48"
+        "commit": "98863b317ab0d038631763dcc66545a26c44f785"
     },
     {
         "name": "libsystemctlm-soc",

examples/old_umiram/test.py

@@ -129,7 +129,7 @@ def python_intf(from_client, to_client, old=True):
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/python/test.py

@@ -74,7 +74,7 @@ def main(client2rtl='client2rtl.q', rtl2client='rtl2client.q', fast=False):
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/router/test.py

@@ -41,7 +41,7 @@ def start_router(aq, bq, cq, dq):
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/stream/test.py

@@ -33,7 +33,7 @@ def main():
 def build_testbench():
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/umi_endpoint/test.py

@@ -83,7 +83,7 @@ def main(client2rtl="client2rtl.q", rtl2client="rtl2client.q", fast=False):
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/umi_endpoint/testbench.sv

@@ -50,7 +50,7 @@ module testbench (
     wire [2:0]    loc_size;
     wire [7:0]    loc_len;
     wire [DW-1:0] loc_wrdata;
-    wire [DW-1:0] loc_rddata;
+    reg  [DW-1:0] loc_rddata;
     wire          loc_ready;
 
     assign loc_ready = nreset;
@@ -70,7 +70,9 @@ module testbench (
 
     reg [63:0] mem [256];
 
-    assign loc_rddata = {192'd0, mem[loc_addr[7:0]]};
+    always @(posedge clk) begin
+        loc_rddata <= {192'd0, mem[loc_addr[7:0]]};
+    end
 
     always @(posedge clk or negedge nreset) begin
         if (!nreset) begin

examples/umi_fifo/test.py

@@ -43,33 +43,17 @@ def main(client2rtl='client2rtl.q', rtl2client='rtl2client.q', n=3, fast=False):
             if rxp is not None:
                 print('* RX *')
                 print(str(rxp))
-                if not packets_match(rxp, txq[0]):
+                if rxp != txq[0]:
                     raise Exception('Mismatch!')
                 else:
                     txq.pop(0)
                     n_recv += 1
 
 
-def packets_match(txp, rxp):
-    # compare data in both packets
-    txbytes = len(txp.data) if txp.data is not None else 0
-    rxbytes = len(rxp.data) if rxp.data is not None else 0
-    if rxbytes != txbytes:
-        data_match = False
-    elif (rxbytes == 0) and (txbytes == 0):
-        data_match = True
-    else:
-        data_match = (txp.data == rxp.data).all()
-
-    # compare the rest of the packets
-    return ((txp.cmd == rxp.cmd) and (txp.dstaddr == rxp.dstaddr)
-        and (txp.srcaddr == rxp.srcaddr) and data_match)
-
-
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/umi_fifo/testbench.sv

@@ -28,7 +28,7 @@ module testbench (
         .srcaddr(udev_req_srcaddr),
         .dstaddr(udev_req_dstaddr),
         .cmd(udev_req_cmd),
-        .ready(udev_req_ready & nreset),
+        .ready(udev_req_ready),
         .valid(udev_req_valid)
     );
 
@@ -39,11 +39,10 @@ module testbench (
         .dstaddr(udev_resp_dstaddr),
         .cmd(udev_resp_cmd),
         .ready(udev_resp_ready),
-        .valid(udev_resp_valid & nreset)
+        .valid(udev_resp_valid)
     );
 
     wire nreset;
-    wire nreset_early;
 
     umi_fifo #(
         .DW(DW),
@@ -55,22 +54,22 @@ module testbench (
         .fifo_full(),
         .fifo_empty(),
         .umi_in_clk(clk),
-        .umi_in_nreset(nreset_early),
-        .umi_in_valid(udev_req_valid & nreset),
+        .umi_in_nreset(nreset),
+        .umi_in_valid(udev_req_valid),
         .umi_in_cmd(udev_req_cmd),
         .umi_in_dstaddr(udev_req_dstaddr),
         .umi_in_srcaddr(udev_req_srcaddr),
         .umi_in_data(udev_req_data),
         .umi_in_ready(udev_req_ready),
         // Output
         .umi_out_clk(clk),
-        .umi_out_nreset(nreset_early),
+        .umi_out_nreset(nreset),
         .umi_out_valid(udev_resp_valid),
         .umi_out_cmd(udev_resp_cmd),
         .umi_out_dstaddr(udev_resp_dstaddr),
         .umi_out_srcaddr(udev_resp_srcaddr),
         .umi_out_data(udev_resp_data),
-        .umi_out_ready(udev_resp_ready & nreset),
+        .umi_out_ready(udev_resp_ready),
         // Supplies
         .vdd(1'b1),
         .vss(1'b0)
@@ -84,7 +83,6 @@ module testbench (
     // TODO: investigate reset sequencing issue
 
     assign nreset = nreset_vec[7];
-    assign nreset_early = nreset_vec[4];
 
     // Initialize UMI
 

examples/umi_fifo_flex/test.py

@@ -3,10 +3,9 @@
 # Example illustrating how to interact with the umi_fifo_flex module
 # Copyright (C) 2023 Zero ASIC
 
-import numpy as np
 from pathlib import Path
 from argparse import ArgumentParser
-from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run, random_umi_packet
+from switchboard import SbDut, UmiTxRx, delete_queue, verilator_run, umi_loopback
 
 
 def main(client2rtl="client2rtl.q", rtl2client="rtl2client.q", n=3, fast=False):
@@ -24,45 +23,13 @@ def main(client2rtl="client2rtl.q", rtl2client="rtl2client.q", n=3, fast=False):
     umi = UmiTxRx(client2rtl, rtl2client)
 
     # randomly write data
-
-    q = []
-    partial = None
-    num_sent = 0
-    num_recv = 0
-
-    while (num_sent < n) or (num_recv < n):
-        # send data
-        if num_sent < n:
-            txp = random_umi_packet()
-            if umi.send(txp, blocking=False):
-                print('*** SENT ***')
-                print(txp)
-                q.append(txp.data)
-                num_sent += 1
-
-        # receive data
-        if num_recv < n:
-            rxp = umi.recv(blocking=False)
-            if rxp is not None:
-                print("*** RECEIVED ***")
-                print(rxp)
-
-                if partial is None:
-                    partial = rxp.data
-                else:
-                    partial = np.concatenate((partial, rxp.data))
-
-                if (len(q) > 0) and (len(q[0]) == len(partial)):
-                    assert (q[0] == partial).all(), "Data mismatch"
-                    q.pop(0)
-                    partial = None
-                    num_recv += 1
+    umi_loopback(umi, n)
 
 
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/umi_splitter/test.py

@@ -65,7 +65,7 @@ def main(in_="in.q", out0="out0.q", out1="out1.q", n=3, fast=False):
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')

examples/umiram/test.py

@@ -92,7 +92,7 @@ def python_intf(from_client, to_client, old=False):
 def build_testbench(fast=False):
     dut = SbDut('testbench')
 
-    EX_DIR = Path('..')
+    EX_DIR = Path('..').resolve()
 
     # Set up inputs
     dut.input('testbench.sv')