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Merge with upstream #271

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merged 58 commits into from
Dec 20, 2024
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04a3736
pulley: Refactor conditional branches and table codegen (#9794)
alexcrichton Dec 12, 2024
e130721
pulley: Get `fused.wast` passing (#9797)
alexcrichton Dec 12, 2024
737243f
cranelift: Round inline stack probes down, not up (#8397)
jameysharp Dec 12, 2024
5b84c89
Update minimal build documentation (#9802)
alexcrichton Dec 12, 2024
0058cb7
pulley: Get strings.wast test passing (#9801)
alexcrichton Dec 12, 2024
30596e6
cli: add http outgoing body options (#9800)
iawia002 Dec 12, 2024
a6eb6f0
Fix some `--target` mistakes from #9802 (#9805)
alexcrichton Dec 12, 2024
ef9c954
pulley: Fill out remaining 32/64-bit integer operations (#9803)
alexcrichton Dec 12, 2024
3ec924f
pulley: Implement float<->int conversions (#9804)
alexcrichton Dec 12, 2024
74cba58
Update to WASI 0.2.3 WIT files (#9807)
sunfishcode Dec 12, 2024
f138aaa
pulley: Implement fcopysign for issue4890.wast (#9810)
minirop Dec 12, 2024
5a646ad
pulley: Move `fp`/`lr` out of `XReg` set (#9806)
alexcrichton Dec 13, 2024
c2e9a5d
pulley: Implement float arithmetic operations (#9808)
alexcrichton Dec 13, 2024
a30dce2
pulley: Get call_indirect.wast spec test working (#9809)
alexcrichton Dec 13, 2024
d68cb17
Exclude Pulley from MIRI testing on PRs (#9816)
alexcrichton Dec 13, 2024
c18ca21
pulley: Get `f{32,64}_bitwise.wast` tests working (#9814)
alexcrichton Dec 13, 2024
cc0df2f
pulley: Get `switch.wast` spec test passing (#9815)
alexcrichton Dec 13, 2024
b4a6d99
pulley: Fill out `bnot` lowering (#9817)
alexcrichton Dec 13, 2024
da93f64
pulley: Fill out lowerings for `{s,u}{min,max}` (#9819)
alexcrichton Dec 14, 2024
9fd2b3a
pulley: Disable the WebAssembly `threads` proposal (#9818)
alexcrichton Dec 14, 2024
128decd
pulley: Initial scaffold of SIMD support (#9820)
alexcrichton Dec 14, 2024
54236e0
Pulley: implement support for `bmask` (#9827)
fitzgen Dec 15, 2024
b10dc29
pulley: Run many existing `*.clif` runtests (#9825)
alexcrichton Dec 16, 2024
e4abe55
[DWARF] Make the GC of child tags conservative by default (#9829)
SingleAccretion Dec 16, 2024
1956401
docs: remove old features flag from bindgen documentation (#9824)
benbrandt Dec 16, 2024
6ed283f
pulley: Lower `umulhi` and `smulhi` in CLIF (#9830)
alexcrichton Dec 16, 2024
392df4a
pulley: Implement `return_call` instructions (#9834)
alexcrichton Dec 16, 2024
d3f05ee
allow customizing log prefixes for wasmtime serve command (#9821)
jzhn Dec 16, 2024
db4bd21
pulley: Implement SIMD `splat` instruction (#9832)
alexcrichton Dec 17, 2024
1f27065
pulley: Get simd_align.wast test passing (#9838)
alexcrichton Dec 17, 2024
a5ae223
pulley: Get `simd_bitwise.wast` test passing (#9839)
alexcrichton Dec 17, 2024
de17231
Update lang-ruby.md (#9841)
zeevick10 Dec 17, 2024
b2f160c
pulley: Get `simd_boolean.wast` test passing (#9840)
alexcrichton Dec 17, 2024
031a28a
aarch64: support udiv for 32bit integers (#9798)
MarinPostma Dec 17, 2024
c547988
pulley: Get `simd_conversions.wast` test working (#9842)
alexcrichton Dec 17, 2024
e2c22d5
pulley: Implement simd `extractlane` CLIF lowering (#9843)
alexcrichton Dec 17, 2024
0758679
pulley: Implement CLIF lowering of `insertlane` (#9844)
alexcrichton Dec 17, 2024
a0676c6
Move memories first in `VMContext` (#9847)
alexcrichton Dec 18, 2024
c817ab1
pulley: Add basic i128 comparison to backend (#9833)
alexcrichton Dec 18, 2024
1ba6b66
Optimize constant offset loads/stores in translation (#9845)
alexcrichton Dec 18, 2024
56db1b6
pulley: Implement `scalar_to_vector` CLIF lowering (#9852)
alexcrichton Dec 18, 2024
8d77205
pulley: Fold `iadd a, $N` into amode (#9846)
alexcrichton Dec 18, 2024
11e238e
pulley: Implement integer vector comparisons (#9853)
alexcrichton Dec 18, 2024
c1d405c
pulley: Shuffle opcodes to free some 1-byte opcodes (#9854)
alexcrichton Dec 18, 2024
b3ac63a
pulley: Add add/sub-with immediate opcodes (#9859)
alexcrichton Dec 18, 2024
ab325dc
Add Default and Debug impls to SparseMap (#9860)
wtachau Dec 18, 2024
7f45649
pulley: Add offset8 integer loads/stores (#9858)
alexcrichton Dec 18, 2024
7a05ab0
pulley: Remove unwind metadata from Cranelift backend (#9862)
alexcrichton Dec 19, 2024
1e4c470
pulley: Add immediate payloads to more opcodes (#9861)
alexcrichton Dec 19, 2024
4178766
pulley: Add branch-with-compare-against-immediate (#9863)
alexcrichton Dec 19, 2024
e4c27ae
pulley: Add macro instructions for function prologue/epilogue (#9864)
alexcrichton Dec 19, 2024
c81b6a9
pulley: Implement simd vector negation (#9865)
alexcrichton Dec 19, 2024
71ca453
[DWARF] Fix debug intrinsics on Linux (#9866)
SingleAccretion Dec 19, 2024
a179f95
cranelift: 32bit div_s, rem_u, rem_s for aarch64 (#9850)
MarinPostma Dec 19, 2024
68976ba
pulley: Fix mistakes in compare-with-immediate (#9870)
alexcrichton Dec 20, 2024
99c5eb8
pulley: Implement some float simd ops (#9869)
alexcrichton Dec 20, 2024
adcaed3
pulley: Use immediate-taking instructions more (#9871)
alexcrichton Dec 20, 2024
8213d9b
Merge with upstream
dhil Dec 20, 2024
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4 changes: 2 additions & 2 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -240,7 +240,6 @@ jobs:
fi
if grep -q pulley names.log; then
echo test-nightly=true >> $GITHUB_OUTPUT
echo test-miri=true >> $GITHUB_OUTPUT
fi
fi
matrix="$(node ./ci/build-test-matrix.js ./commits.log ./names.log $run_full)"
Expand Down Expand Up @@ -876,7 +875,8 @@ jobs:
# workaround for https://bugs.launchpad.net/ubuntu/+source/llvm-defaults/+bug/1972855
sudo mkdir -p /usr/lib/local/lib/python3.10/dist-packages/lldb
sudo ln -s /usr/lib/llvm-15/lib/python3.10/dist-packages/lldb/* /usr/lib/python3/dist-packages/lldb/
cargo test --test all -- --ignored --test-threads 1 debug::
# Only testing release since it is more likely to expose issues with our low-level symbol handling.
cargo test --release --test all -- --ignored --test-threads 1 debug::
env:
LLDB: lldb-15 # override default version, 14

Expand Down
10 changes: 9 additions & 1 deletion Cargo.lock

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

2 changes: 2 additions & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -237,6 +237,7 @@ wasi-common = { path = "crates/wasi-common", version = "=29.0.0", default-featur
wasmtime-fuzzing = { path = "crates/fuzzing" }
wasmtime-jit-icache-coherence = { path = "crates/jit-icache-coherence", version = "=29.0.0" }
wasmtime-wit-bindgen = { path = "crates/wit-bindgen", version = "=29.0.0" }
wasmtime-math = { path = "crates/math", version = "=29.0.0" }
test-programs-artifacts = { path = 'crates/test-programs/artifacts' }

pulley-interpreter = { path = 'pulley', version = "=29.0.0" }
Expand Down Expand Up @@ -356,6 +357,7 @@ rustc-hash = "2.0.0"
libtest-mimic = "0.7.0"
semver = { version = "1.0.17", default-features = false }
ittapi = "0.4.0"
libm = "0.2.7"

# =============================================================================
#
Expand Down
26 changes: 13 additions & 13 deletions ci/vendor-wit.sh
Original file line number Diff line number Diff line change
Expand Up @@ -37,22 +37,22 @@ make_vendor() {
cache_dir=$(mktemp -d)

make_vendor "wasi" "
cli@v0.2.2
clocks@v0.2.2
filesystem@v0.2.2
io@v0.2.2
random@v0.2.2
sockets@v0.2.2
cli@v0.2.3
clocks@v0.2.3
filesystem@v0.2.3
io@v0.2.3
random@v0.2.3
sockets@v0.2.3
"

make_vendor "wasi-http" "
cli@v0.2.2
clocks@v0.2.2
filesystem@v0.2.2
io@v0.2.2
random@v0.2.2
sockets@v0.2.2
http@v0.2.2
cli@v0.2.3
clocks@v0.2.3
filesystem@v0.2.3
io@v0.2.3
random@v0.2.3
sockets@v0.2.3
http@v0.2.3
"

make_vendor "wasi-config" "config@f4d699b"
Expand Down
3 changes: 3 additions & 0 deletions cranelift/bitset/src/scalar.rs
Original file line number Diff line number Diff line change
Expand Up @@ -556,14 +556,17 @@ pub trait ScalarBitSetStorage:
macro_rules! impl_storage {
( $int:ty ) => {
impl ScalarBitSetStorage for $int {
#[inline]
fn leading_zeros(self) -> u8 {
u8::try_from(self.leading_zeros()).unwrap()
}

#[inline]
fn trailing_zeros(self) -> u8 {
u8::try_from(self.trailing_zeros()).unwrap()
}

#[inline]
fn count_ones(self) -> u8 {
u8::try_from(self.count_ones()).unwrap()
}
Expand Down
90 changes: 69 additions & 21 deletions cranelift/codegen/meta/src/pulley.rs
Original file line number Diff line number Diff line change
Expand Up @@ -27,23 +27,52 @@ const OPS: &[Inst<'_>] = pulley_interpreter::for_each_op!(define);
const EXTENDED_OPS: &[Inst<'_>] = pulley_interpreter::for_each_extended_op!(define);

enum Operand<'a> {
Normal { name: &'a str, ty: &'a str },
Writable { name: &'a str, ty: &'a str },
TrapCode { name: &'a str, ty: &'a str },
Binop { reg: &'a str },
Normal {
name: &'a str,
ty: &'a str,
},
Writable {
name: &'a str,
ty: &'a str,
},
TrapCode {
name: &'a str,
ty: &'a str,
},
Binop {
dst: &'a str,
src1: &'a str,
src2: &'a str,
},
}

impl Inst<'_> {
fn operands(&self) -> impl Iterator<Item = Operand<'_>> {
self.fields
.iter()
.map(|(name, ty)| match (*name, *ty) {
("operands", "BinaryOperands < XReg >") => Operand::Binop { reg: "XReg" },
("operands", binop) => {
// Parse "BinaryOperands < A >"` as A/A/A
// Parse "BinaryOperands < A, B >"` as A/B/A
// Parse "BinaryOperands < A, B, C >"` as A/B/C
let mut parts = binop
.strip_prefix("BinaryOperands <")
.unwrap()
.strip_suffix(">")
.unwrap()
.trim()
.split(',')
.map(|x| x.trim());
let dst = parts.next().unwrap();
let src1 = parts.next().unwrap_or(dst);
let src2 = parts.next().unwrap_or(dst);
Operand::Binop { dst, src1, src2 }
}
("dst", ty) => Operand::Writable { name, ty },
(name, "RegSet < XReg >") => Operand::Normal {
name,
ty: "VecXReg",
ty: "XRegSet",
},
("dst", ty) => Operand::Writable { name, ty },
(name, ty) => Operand::Normal { name, ty },
})
.chain(if self.name.contains("Trap") {
Expand Down Expand Up @@ -95,10 +124,17 @@ pub fn generate_rust(filename: &str, out_dir: &Path) -> Result<(), Error> {
if i > 0 {
format_string.push_str(",");
}

if ty == "XRegSet" {
format_string.push_str(" {");
format_string.push_str(name);
format_string.push_str(":?}");
continue;
}

format_string.push_str(" {");
format_string.push_str(name);
format_string.push_str("}");

if ty.contains("Reg") {
if name == "dst" {
locals.push_str(&format!("let {name} = reg_name(*{name}.to_reg());\n"));
Expand All @@ -112,12 +148,14 @@ pub fn generate_rust(filename: &str, out_dir: &Path) -> Result<(), Error> {
pat.push_str(",");
format_string.push_str(&format!(" // trap={{{name}:?}}"));
}
Operand::Binop { reg: _ } => {
Operand::Binop { src2, .. } => {
pat.push_str("dst, src1, src2,");
format_string.push_str(" {dst}, {src1}, {src2}");
locals.push_str(&format!("let dst = reg_name(*dst.to_reg());\n"));
locals.push_str(&format!("let src1 = reg_name(**src1);\n"));
locals.push_str(&format!("let src2 = reg_name(**src2);\n"));
if src2.contains("Reg") {
locals.push_str(&format!("let src2 = reg_name(**src2);\n"));
}
}
}
}
Expand Down Expand Up @@ -149,6 +187,13 @@ pub fn generate_rust(filename: &str, out_dir: &Path) -> Result<(), Error> {
let mut defs = Vec::new();
for op in inst.operands() {
match op {
// `{Push,Pop}Frame{Save,Restore}` doesn't participate in
// register allocation.
Operand::Normal {
name: _,
ty: "XRegSet",
} if *name == "PushFrameSave" || *name == "PopFrameRestore" => {}

Operand::Normal { name, ty } => {
if ty.contains("Reg") {
uses.push(name);
Expand All @@ -164,11 +209,14 @@ pub fn generate_rust(filename: &str, out_dir: &Path) -> Result<(), Error> {
}
}
Operand::TrapCode { .. } => {}
Operand::Binop { reg: _ } => {
pat.push_str("dst, src1, src2,");
Operand::Binop { src2, .. } => {
pat.push_str("dst, src1,");
uses.push("src1");
uses.push("src2");
defs.push("dst");
if src2.contains("Reg") {
pat.push_str("src2,");
uses.push("src2");
}
}
}
}
Expand Down Expand Up @@ -224,7 +272,7 @@ pub fn generate_rust(filename: &str, out_dir: &Path) -> Result<(), Error> {
pat.push_str(",");
trap.push_str(&format!("sink.add_trap({name});\n"));
}
Operand::Binop { reg: _ } => {
Operand::Binop { .. } => {
pat.push_str("dst, src1, src2,");
args.push_str(
"pulley_interpreter::regs::BinaryOperands::new(dst, src1, src2),",
Expand Down Expand Up @@ -268,10 +316,10 @@ pub fn generate_isle(filename: &str, out_dir: &Path) -> Result<(), Error> {
Operand::Writable { name, ty } => {
isle.push_str(&format!("\n ({name} Writable{ty})"));
}
Operand::Binop { reg } => {
isle.push_str(&format!("\n (dst Writable{reg})"));
isle.push_str(&format!("\n (src1 {reg})"));
isle.push_str(&format!("\n (src2 {reg})"));
Operand::Binop { dst, src1, src2 } => {
isle.push_str(&format!("\n (dst Writable{dst})"));
isle.push_str(&format!("\n (src1 {src1})"));
isle.push_str(&format!("\n (src2 {src2})"));
}
}
}
Expand Down Expand Up @@ -306,13 +354,13 @@ pub fn generate_isle(filename: &str, out_dir: &Path) -> Result<(), Error> {
assert!(result.is_none(), "{} has >1 result", inst.snake_name);
result = Some(ty);
}
Operand::Binop { reg } => {
isle.push_str(&format!("{reg} {reg}"));
Operand::Binop { dst, src1, src2 } => {
isle.push_str(&format!("{src1} {src2}"));
rule.push_str("src1 src2");
ops.push("src1");
ops.push("src2");
assert!(result.is_none(), "{} has >1 result", inst.snake_name);
result = Some(reg);
result = Some(dst);
}
}
isle.push_str(" ");
Expand Down
22 changes: 21 additions & 1 deletion cranelift/codegen/src/ir/immediates.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ use core::fmt::{self, Display, Formatter};
use core::ops::{Add, BitAnd, BitOr, BitXor, Div, Mul, Neg, Not, Sub};
use core::str::FromStr;
use core::{i32, u32};
use cranelift_entity::{Signed, Unsigned};
#[cfg(feature = "enable-serde")]
use serde_derive::{Deserialize, Serialize};

Expand Down Expand Up @@ -92,7 +93,7 @@ impl Imm64 {
/// Sign extend this immediate as if it were a signed integer of the given
/// power-of-two width.
#[must_use]
pub(crate) fn sign_extend_from_width(&self, bit_width: u32) -> Self {
pub fn sign_extend_from_width(&self, bit_width: u32) -> Self {
debug_assert!(
bit_width.is_power_of_two(),
"{bit_width} is not a power of two"
Expand All @@ -107,6 +108,25 @@ impl Imm64 {
let sign_extended = (self.0 << delta) >> delta;
Imm64(sign_extended)
}

/// Zero extend this immediate as if it were an unsigned integer of the
/// given power-of-two width.
#[must_use]
pub fn zero_extend_from_width(&self, bit_width: u32) -> Self {
debug_assert!(
bit_width.is_power_of_two(),
"{bit_width} is not a power of two"
);

if bit_width >= 64 {
return *self;
}

let bit_width = u64::from(bit_width);
let delta = 64 - bit_width;
let zero_extended = (self.0.unsigned() << delta) >> delta;
Imm64(zero_extended.signed())
}
}

impl From<Imm64> for i64 {
Expand Down
8 changes: 6 additions & 2 deletions cranelift/codegen/src/isa/aarch64/abi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -705,8 +705,12 @@ impl ABIMachineSpec for AArch64MachineDeps {
// Set this to 3 to keep the max size of the probe to 6 instructions.
const PROBE_MAX_UNROLL: u32 = 3;

let probe_count = align_to(frame_size, guard_size) / guard_size;
if probe_count <= PROBE_MAX_UNROLL {
// Calculate how many probes we need to perform. Round down, as we only
// need to probe whole guard_size regions we'd otherwise skip over.
let probe_count = frame_size / guard_size;
if probe_count == 0 {
// No probe necessary
} else if probe_count <= PROBE_MAX_UNROLL {
Self::gen_probestack_unroll(insts, guard_size, probe_count)
} else {
Self::gen_probestack_loop(insts, frame_size, guard_size)
Expand Down
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