Merge with upstream (#274)

.github/workflows/main.yml

@@ -561,6 +561,12 @@ jobs:
         - target: wasm32-wasip1
           os: ubuntu-latest
           test: cargo build --no-default-features --features compile,cranelift,all-arch
+        - target: aarch64-apple-ios
+          os: macos-latest
+          test: cargo build
+          env:
+            IPHONEOS_DEPLOYMENT_TARGET: 13.0
+    env: ${{ matrix.env || fromJSON('{}') }}
     steps:
     - uses: actions/checkout@v4
       with:

cranelift/codegen/src/isa/pulley_shared/lower.isle

@@ -756,6 +756,9 @@
 (rule (lower (fcmp cc a b @ (value_type (ty_scalar_float ty))))
   (lower_fcmp ty cc a b))
 
+(rule 1 (lower (fcmp cc a b @ (value_type (ty_vec128 ty))))
+  (lower_vfcmp ty cc a b))
+
 (decl lower_fcmp (Type FloatCC Value Value) XReg)
 
 (rule (lower_fcmp $F32 (FloatCC.Equal) a b) (pulley_feq32 a b))
@@ -787,6 +790,32 @@
   (if-let true (floatcc_unordered cc))
   (pulley_xbxor32_s8 (lower_fcmp ty (floatcc_complement cc) a b) 1))
 
+(decl lower_vfcmp (Type FloatCC Value Value) VReg)
+
+(rule (lower_vfcmp $F32X4 (FloatCC.Equal) a b) (pulley_veqf32x4 a b))
+(rule (lower_vfcmp $F64X2 (FloatCC.Equal) a b) (pulley_veqf64x2 a b))
+(rule (lower_vfcmp $F32X4 (FloatCC.NotEqual) a b) (pulley_vneqf32x4 a b))
+(rule (lower_vfcmp $F64X2 (FloatCC.NotEqual) a b) (pulley_vneqf64x2 a b))
+(rule (lower_vfcmp $F32X4 (FloatCC.LessThan) a b) (pulley_vltf32x4 a b))
+(rule (lower_vfcmp $F64X2 (FloatCC.LessThan) a b) (pulley_vltf64x2 a b))
+(rule (lower_vfcmp $F32X4 (FloatCC.LessThanOrEqual) a b) (pulley_vlteqf32x4 a b))
+(rule (lower_vfcmp $F64X2 (FloatCC.LessThanOrEqual) a b) (pulley_vlteqf64x2 a b))
+
+(rule (lower_vfcmp ty (FloatCC.Unordered) a b)
+  (pulley_vbor128
+    (lower_vfcmp ty (FloatCC.NotEqual) a a)
+    (lower_vfcmp ty (FloatCC.NotEqual) b b)))
+
+;; NB: Pulley doesn't have lowerings for `Ordered` or `Unordered*` `FloatCC`
+;; conditions as that's not needed by wasm at this time.
+
+;; Pulley doesn't have instructions for `>` and `>=`, so we have to reverse the
+;; operation.
+(rule (lower_vfcmp ty (FloatCC.GreaterThan) a b)
+  (lower_vfcmp ty (FloatCC.LessThan) b a))
+(rule (lower_vfcmp ty (FloatCC.GreaterThanOrEqual) a b)
+  (lower_vfcmp ty (FloatCC.LessThanOrEqual) b a))
+
 ;;;; Rules for `load` and friends ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl amode (Value Offset32) Amode)
@@ -1203,6 +1232,7 @@
       (pulley_vfloor32x4 a))
 (rule (lower (has_type $F64X2 (floor a)))
       (pulley_vfloor64x2 a))
+
 ;;;; Rules for `ceil` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $F32 (ceil a))) (pulley_fceil32 a))
@@ -1230,7 +1260,6 @@
 (rule (lower (has_type $F64X2 (sqrt a)))
       (pulley_vsqrt64x2 a))
 
-
 ;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $F32 (fneg a))) (pulley_fneg32 a))
@@ -1407,11 +1436,16 @@
 (rule (lower (scalar_to_vector a @ (value_type $F64)))
   (pulley_vinsertf64 (pulley_vconst128 0) a 0))
 
-;;;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule (lower (has_type $I8X16 (shuffle a b (u128_from_immediate mask))))
   (pulley_vshuffle a b mask))
 
 ;;;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule 1 (lower (has_type $I8X16 (swizzle a b))) (pulley_vswizzlei8x16 a b))
+
+;;;; Rules for `fma` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $F32X4 (fma a b c))) (pulley_vfma32x4 a b c))
+(rule (lower (has_type $F64X2 (fma a b c))) (pulley_vfma64x2 a b c))

cranelift/filetests/filetests/runtests/simd-fadd-splat.clif

@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %splat_f32x4_2(f32x4) -> f32x4 {
 block0(v0: f32x4):

cranelift/filetests/filetests/runtests/simd-fadd.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %fadd_f32x4(f32x4, f32x4) -> f32x4 {

cranelift/filetests/filetests/runtests/simd-fcmp-eq.clif

@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %simd_fcmp_eq_f32(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):

cranelift/filetests/filetests/runtests/simd-fcmp-ge.clif

@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %simd_fcmp_ge_f32(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):

cranelift/filetests/filetests/runtests/simd-fcmp-gt.clif

@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %simd_fcmp_gt_f32(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):

cranelift/filetests/filetests/runtests/simd-fcmp-le.clif

@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %simd_fcmp_le_f32(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):

cranelift/filetests/filetests/runtests/simd-fcmp-lt.clif

@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %simd_fcmp_lt_f32(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):

cranelift/filetests/filetests/runtests/simd-fcmp-ne.clif

@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %simd_fcmp_ne_f32(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):

cranelift/filetests/filetests/runtests/simd-fcmp-uno.clif

@@ -6,6 +6,10 @@ target x86_64 has_sse3 has_ssse3 has_sse41 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %simd_fcmp_uno_f32(f32x4, f32x4) -> i32x4 {
 block0(v0: f32x4, v1: f32x4):

cranelift/filetests/filetests/runtests/simd-fdiv.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %fdiv_f32x4(f32x4, f32x4) -> f32x4 {

cranelift/filetests/filetests/runtests/simd-floor.clif

@@ -9,6 +9,10 @@ target s390x
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %floor_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):

cranelift/filetests/filetests/runtests/simd-fma-neg.clif

@@ -5,6 +5,10 @@ target aarch64
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 ;; This file is not enabled in the interpreter since SIMD fneg is currently broken
 ;; there.

cranelift/filetests/filetests/runtests/simd-fma.clif

@@ -6,6 +6,10 @@ target aarch64
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %fma_f32x4(f32x4, f32x4, f32x4) -> f32x4 {
 block0(v0: f32x4, v1: f32x4, v2: f32x4):

cranelift/filetests/filetests/runtests/simd-fmin-max-pseudo.clif

@@ -6,6 +6,10 @@ target x86_64 skylake
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %fmin_pseudo_f32x4(f32x4, f32x4) -> f32x4 {
 block0(v0:f32x4, v1:f32x4):

cranelift/filetests/filetests/runtests/simd-fmul.clif

@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %fmul_f32x4(f32x4, f32x4) -> f32x4 {

cranelift/filetests/filetests/runtests/simd-fneg.clif

@@ -9,6 +9,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 function %fneg_f32x4(f32x4) -> f32x4 {
 block0(v0: f32x4):

cranelift/filetests/filetests/runtests/simd-fsub.clif

@@ -8,6 +8,10 @@ target x86_64 sse42 has_avx
 set enable_multi_ret_implicit_sret
 target riscv64 has_v
 target riscv64 has_v has_c has_zcb
+target pulley32
+target pulley32be
+target pulley64
+target pulley64be
 
 
 function %fsub_f32x4(f32x4, f32x4) -> f32x4 {

crates/asm-macros/src/lib.rs

@@ -9,7 +9,7 @@
 #![no_std]
 
 cfg_if::cfg_if! {
-    if #[cfg(target_os = "macos")] {
+    if #[cfg(target_vendor = "apple")] {
         #[macro_export]
         macro_rules! asm_func {
             ($name:expr, $body:expr $(, $($args:tt)*)?) => {

crates/fiber/src/stackswitch/aarch64.rs

@@ -22,7 +22,7 @@ use super::wasmtime_fiber_start;
 use wasmtime_asm_macros::asm_func;
 
 cfg_if::cfg_if! {
-    if #[cfg(target_os = "macos")] {
+    if #[cfg(target_vendor = "apple")] {
         macro_rules! paci1716 { () => ("pacib1716\n"); }
         macro_rules! pacisp { () => ("pacibsp\n"); }
         macro_rules! autisp { () => ("autibsp\n"); }

crates/jit-icache-coherence/Cargo.toml

@@ -24,7 +24,7 @@ features = [
     "Win32_System_Diagnostics_Debug",
 ]
 
-[target.'cfg(any(target_os = "linux", target_os = "macos", target_os = "freebsd", target_os = "android"))'.dependencies]
+[target.'cfg(any(target_os = "linux", target_vendor = "apple", target_os = "freebsd", target_os = "android"))'.dependencies]
 libc = { workspace = true }
 
 [features]

crates/math/src/lib.rs

@@ -31,7 +31,7 @@ pub trait WasmFloat {
     fn wasm_nearest(self) -> Self;
     fn wasm_minimum(self, other: Self) -> Self;
     fn wasm_maximum(self, other: Self) -> Self;
-    fn mul_add(self, b: Self, c: Self) -> Self;
+    fn wasm_mul_add(self, b: Self, c: Self) -> Self;
 }
 
 impl WasmFloat for f32 {
@@ -148,9 +148,11 @@ impl WasmFloat for f32 {
         }
     }
     #[inline]
-    fn mul_add(self, b: f32, c: f32) -> f32 {
+    fn wasm_mul_add(self, b: f32, c: f32) -> f32 {
+        // The MinGW implementation of `fma` differs from other platforms, so
+        // favor `libm` there instead.
         #[cfg(feature = "std")]
-        if true {
+        if !(cfg!(windows) && cfg!(target_env = "gnu")) {
             return self.mul_add(b, c);
         }
         libm::fmaf(self, b, c)
@@ -271,9 +273,11 @@ impl WasmFloat for f64 {
         }
     }
     #[inline]
-    fn mul_add(self, b: f64, c: f64) -> f64 {
+    fn wasm_mul_add(self, b: f64, c: f64) -> f64 {
+        // The MinGW implementation of `fma` differs from other platforms, so
+        // favor `libm` there instead.
         #[cfg(feature = "std")]
-        if true {
+        if !(cfg!(windows) && cfg!(target_env = "gnu")) {
             return self.mul_add(b, c);
         }
         libm::fma(self, b, c)

crates/wasmtime/Cargo.toml

@@ -90,7 +90,7 @@ ittapi = { workspace = true, optional = true }
 [target.'cfg(target_os = "linux")'.dependencies]
 memfd = { workspace = true, optional = true }
 
-[target.'cfg(target_os = "macos")'.dependencies]
+[target.'cfg(target_vendor = "apple")'.dependencies]
 mach2 = { workspace = true, optional = true }
 
 [target.'cfg(unix)'.dependencies]

crates/wasmtime/build.rs

@@ -36,6 +36,14 @@ fn build_c_helpers() {
         build.define("FEATURE_DEBUG_BUILTINS", None);
     }
 
+    // On MinGW targets work around a bug in the MinGW compiler described at
+    // https://github.com/bytecodealliance/wasmtime/pull/9688#issuecomment-2573367719
+    if std::env::var("CARGO_CFG_WINDOWS").is_ok()
+        && std::env::var("CARGO_CFG_TARGET_ENV").ok().as_deref() == Some("gnu")
+    {
+        build.define("__USE_MINGW_SETJMP_NON_SEH", None);
+    }
+
     println!("cargo:rerun-if-changed=src/runtime/vm/helpers.c");
     build.file("src/runtime/vm/helpers.c");
     build.compile("wasmtime-helpers");