Add RPXY driver for StandaloneMmPkg

docs/domain_support.md

@@ -41,6 +41,7 @@ has following details:
 * **name** - Name of this domain
 * **assigned_harts** - HARTs assigned to this domain
 * **possible_harts** - HARTs possible in this domain
+* **hartindex_to_context_table** - Contexts corresponding to possible HARTs
 * **regions** - Array of memory regions terminated by a memory region
   with order zero
 * **boot_hartid** - HART id of the HART booting this domain. The domain
@@ -80,6 +81,7 @@ following manner:
   platform support
 * **possible_harts** - All valid HARTs of a RISC-V platform are possible
   HARTs of the ROOT domain
+* **hartindex_to_context_table** - Contexts corresponding to ROOT domain's possible HARTs
 * **regions** - Two memory regions available to the ROOT domain:
   **A)** A memory region to protect OpenSBI firmware from S-mode and U-mode
   **B)** A memory region of **order=__riscv_xlen** allowing S-mode and

firmware/payloads/objects.mk

@@ -10,7 +10,7 @@
 firmware-bins-$(FW_PAYLOAD) += payloads/test.bin
 
 test-y += test_head.o
-test-y += test_main.o
+test-y += test_main.o test_sse.o
 
 %/test.o: $(foreach obj,$(test-y),%/$(obj))
 	$(call merge_objs,$@,$^)

firmware/payloads/test_main.c

@@ -40,7 +40,7 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 	return ret;
 }
 
-static inline void sbi_ecall_console_puts(const char *str)
+void sbi_ecall_console_puts(const char *str)
 {
 	sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
 		  sbi_strlen(str), (unsigned long)str, 0, 0, 0, 0);
@@ -51,10 +51,14 @@ static inline void sbi_ecall_console_puts(const char *str)
 		__asm__ __volatile__("wfi" ::: "memory"); \
 	} while (0)
 
+void test_sse(void);
+
 void test_main(unsigned long a0, unsigned long a1)
 {
 	sbi_ecall_console_puts("\nTest payload running\n");
 
+	test_sse();
+
 	while (1)
 		wfi();
 }

firmware/payloads/test_sse.c

@@ -0,0 +1,226 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_string.h>
+
+struct sse_entry_state {
+	/** Entry program counter */
+	unsigned long pc;
+	/** ra register state */
+	unsigned long ra;
+	/** sp register state */
+	unsigned long sp;
+	/** gp register state */
+	unsigned long gp;
+	/** tp register state */
+	unsigned long tp;
+	/** t0 register state */
+	unsigned long t0;
+	/** t1 register state */
+	unsigned long t1;
+	/** t2 register state */
+	unsigned long t2;
+	/** s0 register state */
+	unsigned long s0;
+	/** s1 register state */
+	unsigned long s1;
+	/** a0 register state */
+	unsigned long a0;
+	/** a1 register state */
+	unsigned long a1;
+	/** a2 register state */
+	unsigned long a2;
+	/** a3 register state */
+	unsigned long a3;
+	/** a4 register state */
+	unsigned long a4;
+	/** a5 register state */
+	unsigned long a5;
+	/** a6 register state */
+	unsigned long a6;
+	/** a7 register state */
+	unsigned long a7;
+	/** s2 register state */
+	unsigned long s2;
+	/** s3 register state */
+	unsigned long s3;
+	/** s4 register state */
+	unsigned long s4;
+	/** s5 register state */
+	unsigned long s5;
+	/** s6 register state */
+	unsigned long s6;
+	/** s7 register state */
+	unsigned long s7;
+	/** s8 register state */
+	unsigned long s8;
+	/** s9 register state */
+	unsigned long s9;
+	/** s10 register state */
+	unsigned long s10;
+	/** s11 register state */
+	unsigned long s11;
+	/** t3 register state */
+	unsigned long t3;
+	/** t4 register state */
+	unsigned long t4;
+	/** t5 register state */
+	unsigned long t5;
+	/** t6 register state */
+	unsigned long t6;
+} __packed;
+
+struct sse_interrupted_state {
+	/** Interrupted program counter */
+	unsigned long pc;
+	/** ra register state */
+	unsigned long ra;
+	/** sp register state */
+	unsigned long sp;
+	/** gp register state */
+	unsigned long gp;
+	/** tp register state */
+	unsigned long tp;
+	/** t0 register state */
+	unsigned long t0;
+	/** t1 register state */
+	unsigned long t1;
+	/** t2 register state */
+	unsigned long t2;
+	/** s0 register state */
+	unsigned long s0;
+	/** s1 register state */
+	unsigned long s1;
+	/** a0 register state */
+	unsigned long a0;
+	/** a1 register state */
+	unsigned long a1;
+	/** a2 register state */
+	unsigned long a2;
+	/** a3 register state */
+	unsigned long a3;
+	/** a4 register state */
+	unsigned long a4;
+	/** a5 register state */
+	unsigned long a5;
+	/** a6 register state */
+	unsigned long a6;
+	/** a7 register state */
+	unsigned long a7;
+	/** s2 register state */
+	unsigned long s2;
+	/** s3 register state */
+	unsigned long s3;
+	/** s4 register state */
+	unsigned long s4;
+	/** s5 register state */
+	unsigned long s5;
+	/** s6 register state */
+	unsigned long s6;
+	/** s7 register state */
+	unsigned long s7;
+	/** s8 register state */
+	unsigned long s8;
+	/** s9 register state */
+	unsigned long s9;
+	/** s10 register state */
+	unsigned long s10;
+	/** s11 register state */
+	unsigned long s11;
+	/** t3 register state */
+	unsigned long t3;
+	/** t4 register state */
+	unsigned long t4;
+	/** t5 register state */
+	unsigned long t5;
+	/** t6 register state */
+	unsigned long t6;
+	/** Exception mode */
+	unsigned long exc_mode;
+};
+
+struct sbi_sse_handler_ctx {
+	struct sse_entry_state entry;
+	struct sse_interrupted_state interrupted;
+};
+
+
+#define SBI_ECALL_OUTVAL(__eid, __fid, __a0, __a1, __a2, __outval)            \
+	({                                                                    \
+		register unsigned long a0 asm("a0") = (unsigned long)(__a0);  \
+		register unsigned long a1 asm("a1") = (unsigned long)(__a1);  \
+		register unsigned long a2 asm("a2") = (unsigned long)(__a2);  \
+		register unsigned long a6 asm("a6") = (unsigned long)(__fid); \
+		register unsigned long a7 asm("a7") = (unsigned long)(__eid); \
+		asm volatile("ecall"                                          \
+			     : "+r"(a0)                                       \
+			     : "r"(a1), "r"(a2), "r"(a6), "r"(a7)             \
+			     : "memory");                                     \
+		__outval = a1;                                                \
+		a0;                                                           \
+	})
+
+void sbi_ecall_console_puts(const char *str);
+
+static u8 sse_stack[2][1024];
+static int first_time = 1;
+
+static void sse_test_handler(void *arg)
+{
+	unsigned long out;
+	sbi_ecall_console_puts("Handler invoked !\n");
+
+	if (first_time) {
+		first_time = 0;
+		SBI_ECALL_OUTVAL(SBI_EXT_SSE, SBI_EXT_SSE_INJECT,
+				SBI_SSE_EVENT_LOCAL_RAS_0, 0, 0, out);
+	}
+
+	SBI_ECALL_OUTVAL(SBI_EXT_SSE, SBI_EXT_SSE_COMPLETE,
+			       SBI_SSE_EVENT_LOCAL_RAS_0, 0, 0, out);
+
+	out = out;
+}
+
+void test_sse(void)
+{
+	struct sbi_sse_handler_ctx ctx;
+	unsigned long out, ret;
+
+	sbi_memset(&ctx, 0, sizeof(ctx));
+	ctx.entry.pc = (unsigned long)sse_test_handler;
+	ctx.entry.sp = (unsigned long)sse_stack[0];
+
+	sbi_ecall_console_puts("Starting SSE test\n");
+
+	ret = SBI_ECALL_OUTVAL(SBI_EXT_SSE, SBI_EXT_SSE_REGISTER,
+			       SBI_SSE_EVENT_LOCAL_RAS_0, &ctx, 0, out);
+	if (ret) {
+		sbi_ecall_console_puts("SSE Register failed\n");
+		return;
+	}
+
+	ret = SBI_ECALL_OUTVAL(SBI_EXT_SSE, SBI_EXT_SSE_ENABLE,
+			       SBI_SSE_EVENT_LOCAL_RAS_0, 0, 0, out);
+	if (ret) {
+		sbi_ecall_console_puts("SSE Enable failed\n");
+		return;
+	}
+
+	ret = SBI_ECALL_OUTVAL(SBI_EXT_SSE, SBI_EXT_SSE_INJECT,
+			       SBI_SSE_EVENT_LOCAL_RAS_0, 0, 0, out);
+	if (ret) {
+		sbi_ecall_console_puts("SSE Inject failed\n");
+		return;
+	}
+
+	out = out;
+
+	sbi_ecall_console_puts("Finished SSE test\n");
+}

include/sbi/riscv_encoding.h

@@ -91,6 +91,7 @@
 #define IRQ_M_EXT			11
 #define IRQ_S_GEXT			12
 #define IRQ_PMU_OVF			13
+#define IRQ_RASHP_INT			43
 
 #define MIP_SSIP			(_UL(1) << IRQ_S_SOFT)
 #define MIP_VSSIP			(_UL(1) << IRQ_VS_SOFT)
@@ -103,6 +104,11 @@
 #define MIP_MEIP			(_UL(1) << IRQ_M_EXT)
 #define MIP_SGEIP			(_UL(1) << IRQ_S_GEXT)
 #define MIP_LCOFIP			(_UL(1) << IRQ_PMU_OVF)
+#if __riscv_xlen == 64
+#define MIP_RASHP_INTP			(_UL(1) << IRQ_RASHP_INT)
+#else
+#define MIPH_RASHP_INTP			(_UL(1) << (IRQ_RASHP_INT - 32))
+#endif
 
 #define SIP_SSIP			MIP_SSIP
 #define SIP_STIP			MIP_STIP

include/sbi/sbi_domain.h

@@ -12,6 +12,8 @@
 
 #include <sbi/sbi_types.h>
 #include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_domain_context.h>
+#include <sbi/sbi_rpxy.h>
 
 struct sbi_scratch;
 
@@ -176,6 +178,10 @@ struct sbi_domain {
 	char name[64];
 	/** Possible HARTs in this domain */
 	const struct sbi_hartmask *possible_harts;
+	/** Contexts for possible HARTs indexed by hartindex */
+	struct sbi_context *hartindex_to_context_table[SBI_HARTMASK_MAX_BITS];
+	/** rpxy state for possible HARTs indexed by hartindex */
+	struct rpxy_state *hartindex_to_rs_table[SBI_HARTMASK_MAX_BITS];
 	/** Array of memory regions terminated by a region with order zero */
 	struct sbi_domain_memregion *regions;
 	/** HART id of the HART booting this domain */
@@ -200,6 +206,9 @@ extern struct sbi_domain root;
 /** Get pointer to sbi_domain from HART index */
 struct sbi_domain *sbi_hartindex_to_domain(u32 hartindex);
 
+/** Update HART local pointer to point to specified domain */
+void sbi_update_hartindex_to_domain(u32 hartindex, struct sbi_domain *dom);
+
 /** Get pointer to sbi_domain for current HART */
 #define sbi_domain_thishart_ptr() \
 	sbi_hartindex_to_domain(sbi_hartid_to_hartindex(current_hartid()))