Version 4.15

ufrisk · Mar 14, 2024 · ccc7f8c · ccc7f8c
1 parent f4f68fe
commit ccc7f8c
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Showing 8 changed files with 42 additions and 10 deletions.
diff --git a/ZDMA/100T/src/pcileech_pcie_a7x4.sv b/ZDMA/100T/src/pcileech_pcie_a7x4.sv
@@ -346,7 +346,7 @@ module pcileech_tlps128_src128(
     assign tlps_out.tuser[1]    = rxd_valid ? (rxd_eof || (rxf_eof && (rxf_eof_dw <= 1))) : rxf_eof;    // tlast
     assign tlps_out.tuser[8:2]  = rxd_valid ? rxd_bar_hit : rxf_bar_hit;
     assign tlps_out.tlast       = tlps_out.tuser[1];
-    assign tlps_out.tvalid      = rxd_valid || (rxf_valid && !(rxf_sof && rxf_sof_qw)); 
+    assign tlps_out.tvalid      = rxd_valid || (rxf_valid && rxf_eof) || (rxf_valid && !(rxf_sof && rxf_sof_qw)); 
 
     assign tlps_out.tkeepdw[0]  = rxd_valid || rxf_valid;
     assign tlps_out.tkeepdw[1]  = rxd_valid ? (!rxd_eof || rxd_eof_dw) :

diff --git a/ZDMA/100T/src/pcileech_tbx4_100t.xdc b/ZDMA/100T/src/pcileech_tbx4_100t.xdc
@@ -1,3 +1,8 @@
+# SW
+set_property PACKAGE_PIN F21 [get_ports power_sw]
+set_property IOSTANDARD LVCMOS18 [get_ports power_sw]
+set_property PULLTYPE PULLUP [get_ports power_sw]
+
 # LED
 set_property PACKAGE_PIN AA5 [get_ports pcie_led]
 set_property IOSTANDARD LVCMOS18 [get_ports pcie_led]

diff --git a/ZDMA/100T/src/pcileech_tbx4_100t_top.sv b/ZDMA/100T/src/pcileech_tbx4_100t_top.sv
@@ -14,14 +14,17 @@ module pcileech_tbx4_100t_top #(
     // DEVICE IDs as follows:
     parameter       PARAM_DEVICE_ID = 17,
     parameter       PARAM_VERSION_NUMBER_MAJOR = 4,
-    parameter       PARAM_VERSION_NUMBER_MINOR = 14,
-    parameter       PARAM_CUSTOM_VALUE = 32'hffffffff
+    parameter       PARAM_VERSION_NUMBER_MINOR = 15,
+    parameter       PARAM_CUSTOM_VALUE = 32'hffffffff,
+    parameter       POWER_SW_MODE = 0,                 // disable_pcie_on_thunderbolt_noconnect_not_enabled(0), disable_pcie_on_thunderbolt_noconnect_enabled(1)
+    parameter       POWER_SW_TIME = 60*125_000_000     // detection sample time in ticks of 125MHz (125M=1s)
 ) (
     // SYS
     input           clk_in,
 
     // SYSTEM LEDs and BUTTONs
     output          pcie_led,
+    input           power_sw,
 
     // TO/FROM FPGA IO BRIDGE
     input   [36:0]  BUS_DO,
@@ -45,6 +48,7 @@ module pcileech_tbx4_100t_top #(
     wire rst;
     wire clk;
     wire clk_com;
+    reg  rst_sw = 0;
 
     // FIFO CTL <--> COM CTL
     wire [63:0]     com_dout;
@@ -64,7 +68,7 @@ module pcileech_tbx4_100t_top #(
 
     // PCIe
     wire pcie_present = pcie_present1 && pcie_present2;
-    wire pcie_perst_n = pcie_perst1_n && pcie_perst2_n;
+    wire pcie_perst_n = pcie_perst1_n && pcie_perst2_n && ~rst_sw;
 
     // ----------------------------------------------------
     // CLK: INPUT (clkin): 50MHz
@@ -94,7 +98,20 @@ module pcileech_tbx4_100t_top #(
 
     wire            led_pcie;
     OBUF led_ld1_obuf(.O(pcie_led), .I(led_pcie));
-
+
+    // ----------------------------------------------------
+    // POWER SWITCH MODE (DISABLE PCIE WHEN THUNDERBOLT NOT CONNECTED)
+    // ----------------------------------------------------
+
+    always @ ( posedge clk ) begin
+        if ( rst ) begin
+            rst_sw    <= 0;
+        end
+        else if ( (POWER_SW_MODE == 1) && (tickcount64 == POWER_SW_TIME) ) begin
+            rst_sw    <= ~power_sw; 
+        end
+    end
+
     // ----------------------------------------------------
     // BUFFERED COMMUNICATION DEVICE (FPGA IO BRIDGE)
     // ----------------------------------------------------

diff --git a/ZDMA/readme.md b/ZDMA/readme.md
@@ -84,3 +84,9 @@ v4.14
 * Initial Release
 * Download pre-built binaries below:
   * [ZDMA](https://mega.nz/file/gCQ2kKhR#zSKpIP_sfRQ85zdtDwriAb8J9aAifdkCbfjHvPmaSnI) SHA256: `759c5ac97ffe742b38aa0c9ff4f62e49af01f32e9eb85697edf5692b00269475`
+
+v4.15
+* Bug fixes for PCIe x4 interface.
+* Support for disabling device when Thunderbolt is not connected (not enabled in pre-built version).
+* Download pre-built binaries below:
+  * [ZDMA](https://mega.nz/file/pD4XQKZJ#8RTqip8T2yXo1F8N0UgFikl4MEfaxtGotuZVabR_pGo) SHA256: `8084d838d2cd3715ffe52219a6faed599d40f228b0639eacdc337000cf89c419`
diff --git a/ac701_ft601/readme.md b/ac701_ft601/readme.md
@@ -111,13 +111,17 @@ v4.11
 v4.12
 * Bug fixes.
 * Download pre-built binary [here](https://mega.nz/file/haxAFYZR#6oEOklJH4hmyWYW7Ffhj88wdiUoaxVgyIpbEFhS95aY). <br>SHA256: `4581fda04fb681c7d0fe909c156c7c8dcb2c789bb3c0422ade0a973d8962365b`
-</details>
 
 v4.13
 * Bug fixes.
 * New internal design with on-board PIO BAR support.
 * Download pre-built binary [here](https://mega.nz/file/1W4QgILB#t5pBSs2eznL8crm3GgSNRzbk1CSzb3_YSTI5Ok65-Ww) SHA256: `1607eed95b24b470be20b4ea710c0a4d0f446786a7acae939df4b827201cddea`
+</details>
 
 v4.14
 * Bug fixes.
 * Download pre-built binary [here](https://mega.nz/file/AOhiSKDZ#OiQr9rgyWiOMMLE7S_qG3NDKLdRmpHs3tNENtKMw5v0) SHA256: `7d13e2626df82a352df16011ce94d0ca8f3958190fba08facda702f5e0a1916a`
+
+v4.15
+* Bug fixes for PCIe x4 interface.
+* Download pre-built binary [here](https://mega.nz/file/UDYmEYZL#oiF3EvQymhMSwcu1D4JJH8v32vRvNg0_BYZ6GB6wVOw) SHA256: `7b99dc9fd91e8ecc6d97a72919745da2d58d977331cc7334dc0f899cbe93f896`
diff --git a/ac701_ft601/src/pcileech_ac701_ft601_top.sv b/ac701_ft601/src/pcileech_ac701_ft601_top.sv
@@ -13,7 +13,7 @@
 module pcileech_ac701_ft601_top #(
     parameter       PARAM_DEVICE_ID = 2,
     parameter       PARAM_VERSION_NUMBER_MAJOR = 4,
-    parameter       PARAM_VERSION_NUMBER_MINOR = 14,
+    parameter       PARAM_VERSION_NUMBER_MINOR = 15,
     parameter       PARAM_CUSTOM_VALUE = 32'hffffffff
 ) (
     // SYS

diff --git a/ac701_ft601/src/pcileech_pcie_a7x4.sv b/ac701_ft601/src/pcileech_pcie_a7x4.sv
@@ -346,7 +346,7 @@ module pcileech_tlps128_src128(
     assign tlps_out.tuser[1]    = rxd_valid ? (rxd_eof || (rxf_eof && (rxf_eof_dw <= 1))) : rxf_eof;    // tlast
     assign tlps_out.tuser[8:2]  = rxd_valid ? rxd_bar_hit : rxf_bar_hit;
     assign tlps_out.tlast       = tlps_out.tuser[1];
-    assign tlps_out.tvalid      = rxd_valid || (rxf_valid && !(rxf_sof && rxf_sof_qw)); 
+    assign tlps_out.tvalid      = rxd_valid || (rxf_valid && rxf_eof) || (rxf_valid && !(rxf_sof && rxf_sof_qw)); 
 
     assign tlps_out.tkeepdw[0]  = rxd_valid || rxf_valid;
     assign tlps_out.tkeepdw[1]  = rxd_valid ? (!rxd_eof || rxd_eof_dw) :

diff --git a/readme.md b/readme.md
@@ -12,12 +12,12 @@ PCILeech currently supports multiple FPGA based devices with most recent firmwar
 | Device                                | Connection   | Transfer Speed | Version | FPGA         | PCIe Version  | Project<br>Sponsor |
 | ------------------------------------- | ------------ | -------------- | --------| ------------ | ------------- | ------------------ |
 | [Screamer PCIe Squirrel](PCIeSquirrel)| USB-C        | 190 MB/s       | 4.14    | XC7A35T-484  | PCIe gen2 x1  | [💖](https://shop.lambdaconcept.com) |
-| [ZDMA](ZDMA)                          | Thunderbolt3 | 1000 MB/s      | 4.14    | XC7A100T-484 | PCIe gen2 x4  | [💖](https://lightingz.store/) |
+| [ZDMA](ZDMA)                          | Thunderbolt3 | 1000 MB/s      | 4.15    | XC7A100T-484 | PCIe gen2 x4  | [💖](https://lightingz.store/) |
 | [LeetDMA](https://enigma-x1.com/)     | USB-C        | 190 MB/s       | 4.14    | XC7A35T-484  | PCIe gen2 x1  | [💖](https://enigma-x1.com/)         |
 | [Enigma X1](EnigmaX1)                 | USB-C        | 200 MB/s       | 4.14    | XC7A75T-484  | PCIe gen2 x1  | [💖](https://enigma-x1.com/)         |
 | [PCIeScreamerR04](ScreamerM2)         | USB-C        | 190 MB/s       | 4.14    | XC7A35T-325  | PCIe gen2 x4* | [💖](https://shop.lambdaconcept.com) |
 | [ScreamerM2](ScreamerM2)              | USB3/USB-C   | 190 MB/s       | 4.14    | XC7A35T-325  | PCIe gen2 x4* | [💖](https://shop.lambdaconcept.com) |
-| [AC701/FT601](ac701_ft601)            | USB3         | 190 MB/s       | 4.14    | XC7A200T-676 | PCIe gen2 x4  |                    |
+| [AC701/FT601](ac701_ft601)            | USB3         | 190 MB/s       | 4.15    | XC7A200T-676 | PCIe gen2 x4  |                    |
 
 ###### *) PCILeech FPGA uses PCIe x1 even if more PCIe lanes are available hardware-wise. This is sufficient to deliver neccessary performance.