- 👋 Hi, I’m Justin @ucycg
- 👀 I’m interested in Electrical Engineering
- 🌱 I’m currently studying EE Master Degree @ KIT
- I can code mostly in C/C++ and also a little bit of Python
- Also I try to learn VHDL/Verilog as I'm working on a master thesis in Digital Design (Physical Implementation) with Cadence Tools (Xcelium/Genus/Innovus)
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neorv32
neorv32 PublicForked from stnolting/neorv32
🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
VHDL
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astropix-python-LFndry-Test
astropix-python-LFndry-Test PublicForked from nic-str/astropix-python
Python
17 contributions in the last year
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January 2025
Created 1 repository
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ucycg/astropix-python-LFndry-Test
Python
This contribution was made on Jan 20